INTEGRATED DEVICE COMPRISING VIA WITH SIDE BARRIER LAYER TRAVERSING ENCAPSULATION LAYER

• US 20150228556A1
• Filed: 05/09/2014
• Published: 08/13/2015
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Jae Sik, We, Hong Bok, Kim, Dong Wook, Gu, Shiqun
• Granted Patent: US 9,466,554 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1533 the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate

Abstract

Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Claims

1. An integrated device comprising:

an encapsulation layer;

a via structure traversing the encapsulation layer, wherein the via structure comprises;

a via comprising a first side, a second side, and a third side; and

a barrier layer surrounding at least the first side and the third side of the via; and

a pad directly coupled to the barrier layer of the via structure.

2. The integrated device of claim 1, further comprising a first dielectric layer coupled to a first surface of the encapsulation layer.

3. The integrated device of claim 2, further comprising a second dielectric layer coupled to a second surface of the encapsulation layer.

4. The integrated device of claim 1, further comprising a substrate coupled to a first surface of the encapsulation layer.

5. The integrated device of claim 4, further comprising a first die coupled to the substrate, wherein the encapsulation layer encapsulates the first die.

6. The integrated device of claim 4, wherein the via structure further comprises a fill.

7. The integrated device of claim 1, wherein the via comprises a seed layer.

8. The integrated device of claim 1, wherein the via comprises a portion configured to operate as a pad.

9. The integrated device of claim 1, wherein the integrated device comprises one of at least an interposer, a package device, and/or a package-on-package (PoP) device.

10. The integrated device of claim 1, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

11. An apparatus comprising:

an encapsulation layer;

a via structure traversing the encapsulation layer, wherein the via structure comprises;

a via comprising a first side, a second side, and a third side; and

a barrier means surrounding at least the first side and the third side of the via; and

a pad directly coupled to the barrier layer of the via structure.

12. The apparatus of claim 11, further comprising a first dielectric layer coupled to a first surface of the encapsulation layer.

13. The apparatus of claim 12, further comprising a second dielectric layer coupled to a second surface of the encapsulation layer.

14. The apparatus of claim 11, further comprising a substrate coupled to a first surface of the encapsulation layer.

15. The apparatus of claim 14, further comprising a first die coupled to the substrate, wherein the encapsulation layer encapsulates the first die.

16. The apparatus of claim 11, wherein the via structure further comprises a fill means.

17. The apparatus of claim 11, wherein the via comprises a seed layer.

18. The apparatus of claim 11, wherein the via comprises a portion configured to operate as a pad.

19. The apparatus of claim 11, wherein the apparatus comprises one of at least an interposer, a package device, and/or a package-on-package (PoP) device.

20. The apparatus of claim 11, wherein the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

21. A method for fabricating an integrated device, comprising:

forming a pad on a substrate;

forming an encapsulation layer on the substrate; and

forming a via structure in the encapsulation layer, wherein forming the via structure comprises;

forming a barrier layer in the encapsulation layer; and

forming a via on the barrier layer, the via comprising a first side, a second side, and a third side, the via is formed on the barrier layer such that the barrier layer surrounds at least the first side and the third side of the via, wherein the barrier layer is directly coupled to the pad.

22. The method of claim 21, further comprising forming a first dielectric layer on a first surface of the encapsulation layer.

23. The method of claim 22, further comprising forming a second dielectric layer on a second surface of the encapsulation layer.

24. The method of claim 21, further comprising removing at least a portion of the substrate.

25. The method of claim 21, further comprising coupling a first die to the substrate, wherein forming the encapsulation layer comprising encapsulating the first die with the encapsulation layer.

26. The method of claim 21, wherein forming the via structure further comprises forming a fill.

27. The method of claim 21, wherein forming the via comprises forming a seed layer on the barrier layer.

28. The method of claim 21, wherein forming the via comprises forming a portion a via as a pad.

29. The method of claim 21, wherein the integrated device comprises one of at least an interposer, a package device, and/or a package-on-package (PoP) device.

30. The method of claim 21, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.