METHOD FOR SYSTEM FOR MANUFACTURING TFT, TFT, AND ARRAY SUBSTRATE

• US 20150228760A1
• Filed: 12/17/2013
• Published: 08/13/2015
• Est. Priority Date: 07/19/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Ni, Shuibin, Wei, Xiaodan, Yang, Xiaofeng, Jang, Dongkoog
• Granted Patent: US 9,337,312 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67075 for wet etching
• CPC Class Codes: H01L 21/67109 mainly by convection
• CPC Class Codes: H01L 21/67161 characterized by the layout of the process chambers
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/6723 comprising at least one plating chamber electroless plating apparatuses C23C, electroplating apparatuses C25D
• CPC Class Codes: H01L 21/67742 Mechanical parts of transfer devices robots in general in B25J
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.

Claims

1. A method for manufacturing a TFT, comprising a step of forming a pattern of source/drain electrode, a pattern of doped semiconductor layer, and a pattern of semiconductor layer, wherein

the step of forming the pattern of source/drain electrode, the pattern of doped semiconductor layer, and the pattern of semiconductor layer comprises:

forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially, the first patterned photoresist layer covering a region of the pattern of source/drain electrode and a channel region;

performing first etching so as to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer;

performing second etching so as to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer, thereby forming the pattern of semiconductor layer;

performing ashing treatment on the photoresist layer so as to remove the photoresist layer on the channel region;

hard-baking the photoresist layer after the ashing treatment;

performing third etching so as to remove the source/drain electrode film on a region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of source/drain electrode; and

performing fourth etching so as to remove the doped semiconductor film on the region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of doped semiconductor layer.

2. The method according to claim 1, wherein the photoresist layer after the ashing treatment is hard-baked at a temperature of from 50 to 500°

C.

3. The method according to claim 1, wherein the photoresist layer after the ashing treatment is hard-baked for 30 to 600 seconds.

4. The method according to claim 1, wherein an etchant used for the first etching has a concentration less than an etchant used for the third etching.

5. The method according to claim 4, wherein the etchant used for the first etching has a concentration of 20% to 40% of the etchant used for the third etching.

6. The method according to claim 5, wherein the etchant used for the first etching has a concentration of 30% of the etchant used for the third etching.

7. The method according to claim 1, wherein the second etching and the fourth etching are both dry etching.

8. The method according to claim 1, wherein the step of forming the first patterned photoresist layer comprises:

forming a photoresist film on the formed source/drain electrode film, exposing and developing the photoresist film on different regions by a mask exposure process, and removing the photoresist beyond the region of the pattern of source/drain electrode and the channel region, thereby forming the first patterned photoresist layer.

9. The method according to claim 1, wherein subsequent to the fourth etching, the method further comprises peeling off the photoresist layer after the ashing treatment.

10. The method according to claim 1, wherein prior to forming the semiconductor film, the method further comprises forming a pattern of gate electrode and a pattern of gate insulating layer,

the step of forming the pattern of gate electrode comprises:

forming a gate metal film and a second patterned photoresist layer sequentially, the second patterned photoresist layer covering a region of the pattern of gate electrode;

removing the gate metal film that is not covered by the second patterned photoresist layer by etching, thereby forming the pattern of gate electrode; and

peeling off the second patterned photoresist layer, and

the step of forming the pattern of gate insulating layer comprises;

forming a gate insulating film on the pattern of gate electrode, thereby forming the pattern of gate insulating layer.

11. A method for manufacturing an array substrate including several TFTs manufactured by the method according to any one of claims 1 to 10.

12. A TFT, comprising a pattern of source/drain electrode, a pattern of doped semiconductor layer, a pattern of semiconductor layer, a pattern of gate electrode and a pattern of gate insulating layer, wherein

the pattern of gate insulating layer is formed on the pattern of gate electrode, the pattern of semiconductor layer is formed on the pattern of gate insulating layer, the pattern of doped semiconductor layer is formed on the pattern of semiconductor layer, and the pattern of source/drain electrode is formed on the pattern of doped semiconductor layer,

the pattern of source/drain electrode, the pattern of doped semiconductor layer, the pattern of doped semiconductor layer and the pattern of semiconductor layer are formed by:

forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially, the first patterned photoresist layer covering a region of the pattern of source/drain electrode and a channel region;

performing first etching so as to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer;

performing second etching so as to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer, thereby forming the pattern of semiconductor layer;

performing ashing treatment on the photoresist layer so as to remove the photoresist layer on the channel region;

hard-baking the photoresist layer after the ashing treatment;

performing third etching so as to remove the source/drain electrode film on a region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of source/drain electrode; and

performing fourth etching so as to remove the doped semiconductor film on the region that is not covered by the photoresist layer after the ashing treatment, thereby forming the pattern of doped semiconductor layer.

13. The TFT according to claim 12, wherein a gradient angle between a first side surface and a bottom of the pattern of source/drain electrode is less than 90°

, and a gradient angle between a second side surface and the bottom of the pattern of source/drain electrode is less than 90°

.

14. The TFT according to claim 13, wherein both the gradient angles between the first side surface and the bottom of the pattern of source/drain electrode, and between the second side surface and the bottom of the pattern of source/drain electrode, are in the range of 60 to 70°

.

15. An array substrate comprising a glass substrate, a passivation layer, a pixel electrode and a common electrode, wherein the array substrate further comprises the TFT according to claim 12 or 13.

16. A system for manufacturing a TFT, the system being used to machine a to-be-processed workpiece so as to manufacture the TFT, wherein the system comprises a plating device, a photoresist coating device, a wet etching device, a dry etching device, an ashing device, an oven and a mechanical arm, wherein

the plating device is configured to form a semiconductor film, a doped semiconductor film and a source/drain electrode film sequentially on the to-be-processed workpiece,

the photoresist coating device is configured to form a first patterned photoresist layer on the to-be-processed workpiece where the semiconductor film, the doped semiconductor film and the source/drain electrode film have been formed, the first patterned photoresist layer covering a region of a pattern of source/drain electrode and a channel region,

the wet etching device comprises a first wet etching unit and a second wet etching unit, the first wet etching unit is configured to perform first etching so as to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer, and the second wet etching unit is configured to perform third etching so as to remove the source/drain electrode film on a region that is not covered by the photoresist layer after ashing treatment, thereby to form the pattern of source/drain electrode,

the dry etching device comprises a first dry etching unit and a second dry etching unit, the first dry etching unit is configured to perform in second etching so as to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer, thereby to form a pattern of semiconductor layer, and the second dry etching unit is configured to perform fourth etching so as to remove the doped semiconductor film on the region that is not covered by the photoresist layer after the ashing treatment, thereby to form a pattern of doped semiconductor layer,

the ashing device is configured to perform ashing treatment on the photoresist layer so as to remove the photoresist layer on the channel region,

the oven is configured to hard bake the photoresist layer after the ashing treatment, and

the mechanical arm is configured to move the to-be-processed workpiece from the wet etching device to the dry etching device, from the dry etching device to the ashing device, from the ashing device to the oven, and from the oven to the wet etching device.