METHODS OF FORMING CONTACTS TO SEMICONDUCTOR DEVICES USING A BOTTOM ETCH STOP LAYER AND THE RESULTING DEVICES

• US 20150228776A1
• Filed: 02/07/2014
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong
• Application Number:
  US14/175,217
• Publication Number:
  US 20150228776A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

One method disclosed includes, among other things, forming a patterned high-k etch stop layer above source/drain regions, performing at least etching process to form at least one contact opening in a layer of insulating material, wherein the patterned high-k etch stop layer acts as an etch stop during the etching process, performing a second etching process to remove portions of the patterned high-k etch stop layer exposed by the contact opening and forming a conductive contact in the contact opening that is conductively coupled to the source/drain regions. The device includes a patterned high-k etch stop layer positioned between the conductive contact and an outermost sidewall spacer, wherein an outer side surface of the patterned high-k etch stop layer contacts the conductive contact.

Claims

1. A method of forming a transistor above a semiconductor substrate, said transistor comprising a gate structure and an epitaxially formed semiconductor material in source/drain regions of said transistor, wherein the method comprises:

forming a patterned high-k etch stop layer above said epitaxially formed semiconductor material in said source/drain regions of said transistor;

forming at least one layer of insulating material above said patterned high-k etch stop layer;

performing at least one contact opening etching process to form at least one contact opening in said at least one layer of insulating material, wherein said patterned high-k etch stop layer acts as an etch stop during said at least one contact opening etching process;

performing an etching process to remove portions of said patterned high-k etch stop layer exposed by said at least one contact opening; and

forming a conductive contact in said at least one contact opening that is conductively coupled to said epitaxially formed semiconductor material in at least one of said source/drain regions of said transistor.

2. The method of claim 1, wherein forming said patterned high-k etch stop layer above said epitaxially formed semiconductor material in said source/drain regions of said transistor comprises:

forming a high-k etch stop layer above said gate structure and above said epitaxially formed semiconductor material in said source/drain regions of said transistor;

forming a sacrificial layer of material above said gate structure and said high-k etch stop layer;

reducing a thickness of said sacrificial layer of material so as to expose a portion, but not all, of said high-k etch stop layer, said reduced-thickness sacrificial layer of material having an upper surface; and

performing at least one first etching process to remove at least the portions of said high-k etch stop layer positioned above said upper surface of said reduced-thickness sacrificial layer to thereby form said patterned high-k etch stop layer.

3. The method of claim 2, wherein, after performing said at least one first etching process, the method further comprises removing any residual portions of said reduced-thickness sacrificial layer of material.

4. The method of claim 3, wherein, after removing said residual portions of said reduced-thickness sacrificial layer of material, the method further comprises forming at least one layer of insulating material above said patterned high-k etch stop layer.

5. The method of claim 1, further comprising:

prior to forming said patterned high-k etch stop layer, forming a liner layer on said epitaxially formed semiconductor material and on sidewall spacers positioned adjacent said gate structure;

forming a non-patterned layer of said high-k etch stop layer on said liner layer; and

patterning said non-patterned layer of said high-k etch stop layer so as to thereby form said patterned high-k etch stop layer.

6. The method of claim 1, wherein said patterned high-k etch stop layer is formed on and in contact with said epitaxially formed semiconductor material in said source/drain regions.

7. The method of claim 1, wherein said patterned high-k etch stop layer is comprised of one of aluminum oxide or hafnium oxide.

8. The method of claim 5, further comprising performing an etching process through said patterned high-k etch stop layer so as to remove exposed portions of said liner layer and thereby expose portions of said epitaxially formed semiconductor material in said source/drain regions.

9. The method of claim 1, wherein said gate structure is one of a final gate structure or a sacrificial gates structure.

10. A method of forming a transistor above a semiconductor substrate, said transistor comprising a gate structure, sidewall spacers and an epitaxially formed semiconductor material in source/drain regions of said transistor, wherein the method comprises:

forming a high-k etch stop layer above said gate structure and above said epitaxially formed semiconductor material in said source/drain regions of said transistor;

forming a sacrificial layer of material above said gate structure and said high-k etch stop layer;

reducing a thickness of said sacrificial layer of material so as to expose a portion, but not all, of said high-k etch stop layer, said reduced-thickness sacrificial layer of material having an upper surface;

performing at least one first etching process to remove at least the portions of said high-k etch stop layer positioned above said upper surface of said reduced-thickness sacrificial layer, thereby forming a patterned high-k etch stop layer;

after performing said at least one first etching process, removing any residual portions of said reduced-thickness sacrificial layer of material;

after removing said residual portions of said reduced-thickness sacrificial layer of material, forming at least one layer of insulating material above said patterned high-k etch stop layer;

performing at least one second etching process to form at least one contact opening in said at least one layer of insulating material, wherein said patterned high-k etch stop layer acts as an etch stop during said at least one second etching process;

performing a third etching process to remove portions of said patterned high-k etch stop layer exposed by said at least one contact opening; and

forming a conductive contact in said at least one contact opening that is conductively coupled to said epitaxially formed semiconductor material in at least one of said source/drain regions of said transistor.

11. The method of claim 10, further comprising:

prior to forming said high-k etch stop layer, forming a liner layer on said epitaxially formed semiconductor material and on sidewall spacers positioned adjacent said gate structure;

forming said high-k etch stop layer on said liner layer; and

performing at least one etching process using said liner layer as an etch stop layer so as to thereby form said patterned high-k etch stop layer.

12. The method of claim 11, further comprising performing an etching process through said patterned high-k etch stop layer so as to remove exposed portions of said liner layer and thereby expose portions of said epitaxially formed semiconductor material in said source/drain regions.

13. A method of forming a transistor above a semiconductor substrate, said transistor comprising a gate structure and a plurality of source/drain regions, wherein the method comprises:

forming a patterned high-k etch stop layer above said source/drain regions of said transistor;

forming at least one layer of insulating material above said patterned high-k etch stop layer;

performing at least one contact opening etching process to form at least one contact opening in said at least one layer of insulating material, wherein said patterned high-k etch stop layer acts as an etch stop during said at least one contact opening etching process;

performing an etching process to remove portions of said patterned high-k etch stop layer exposed by said at least one contact opening; and

forming a conductive contact in said at least one contact opening that is conductively coupled to at least one of said source/drain regions of said transistor.

14. A transistor device comprising a plurality of source/drain regions, the device comprising:

a gate structure formed above a semiconductor substrate;

a gate cap layer positioned above at least a portion of said gate structure, said gate cap layer having a bottom surface;

an outermost sidewall spacer formed adjacent a side of said gate structure;

a conductive contact that is conductively coupled to one of said source/drain regions; and

a patterned high-k etch stop layer positioned between said conductive contact and said outermost sidewall spacer, wherein an outer side surface of said patterned high-k etch stop layer contacts said conductive contact and an upper surface of said patterned high-k etch stop layer is positioned at a level relative to an upper surface of said semiconductor substrate that is below a level of said bottom surface of said gate cap layer.

15. The device of claim 14, wherein a bottom surface of said patterned high-k etch stop layer contacts an upper surface of said source/drain regions.

16. The device of claim 15, wherein an inner surface of said patterned high-k etch stop layer contacts an outer surface of said outermost sidewall spacer.

17. The device of claim 14, further comprising an epi semiconductor material that is formed as part of said source/drain regions.

18. The device of claim 17, wherein a bottom surface of said patterned high-k etch stop layer contacts an upper surface of said epi semiconductor material.

19. The device of claim 18, wherein an inner surface of said patterned high-k etch stop layer contacts an outer surface of said outermost sidewall spacer.

20. The device of claim 14, wherein the device further comprises a liner layer positioned between said patterned high-k etch stop layer and said outermost sidewall spacer.

21. The device of claim 20, wherein a bottom surface of said patterned high-k etch stop layer contacts an upper surface of said liner layer and a bottom surface of said liner layer contacts an upper surface of said source/drain regions.

22. The device of claim 21, wherein an inner surface of said patterned high-k etch stop layer contacts said liner layer and said liner layer contacts an outer surface of said outermost sidewall spacer.

23. The device of claim 20, further comprising an epi semiconductor material that is formed as part of said source/drain regions.

24. The device of claim 23, wherein a bottom surface of said patterned high-k etch stop layer contacts an upper surface of said liner layer and a bottom surface of said liner layer contacts an upper surface of said epi semiconductor material.

25. The device of claim 24, wherein an inner surface of said patterned high-k etch stop layer contacts said liner layer and said liner layer contacts an outer surface of said outermost sidewall spacer.

26. The device of claim 23, wherein an inner surface of said patterned high-k etch stop layer contacts an outer surface of said outermost sidewall spacer.

27. The device of claim 14, wherein said conductive contact is comprised of a barrier layer and the outer side surface of said patterned high-k etch stop layer contacts said barrier layer.