SILICON ON INSULATOR DEVICE WITH PARTIALLY RECESSED GATE

• US 20150228777A1
• Filed: 02/07/2014
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Granted Patent: US 9,905,648 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Claims

1. A transistor, comprising:

a raised doped source region that extends above a top surface of an active region of a substrate and downward to a buried oxide layer;

a raised doped drain region that extends above the top surface of the active region of the substrate and downward to the buried oxide layer; and

a gate stack partially recessed to a recess depth below the top surface of the active region of the substrate, the gate stack including;

an epitaxial channel extending between the raised source and drain regions;

a high-k gate dielectric in contact with the planar epitaxial channel; and

a metal gate.

2. The transistor of claim 1, further comprising:

an encapsulant surrounding at least three sides of the metal gate; and

metal contacts to the raised source and drain regions.

3. The transistor of claim 1 wherein the recess depth determines one or more capacitances of the transistor.

4. The transistor of claim 1 wherein the epitaxial channel is made of silicon germanium.

5. The transistor of claim 1 wherein the encapsulant determines a gate-to-source/drain capacitance of the transistor.

6. The transistor of claim 1 wherein the recess depth determines a switching speed of the transistor.

7. The transistor of claim 1 wherein the recess depth determines a degree of off-state current leakage of the transistor.

8. The method of claim 1 wherein the high-k gate dielectric is made of a material having a dielectric constant greater than about 4.0.

9. The transistor of claim 1 wherein the metal gate includes a metal barrier seed layer made of a metal silicide that includes one or more of titanium, titanium nitride, titanium carbide, titanium tungsten, tantalum, or tantalum nitride.

10. The transistor of claim 1 wherein the metal gate includes one or more of aluminum, tungsten, silver, platinum, gold, or copper.

11. The transistor of claim 1 wherein the raised doped source and drain regions are doped with negatively charged ions to form an N-type transistor.

12. The transistor of claim 1 wherein the raised doped source and drain regions are doped with positively charged ions to form a P-type transistor, and the transistor further comprises a work function material in contact with the high-k gate dielectric, the work function material including one or more of titanium nitride, titanium carbide, or titanium tungsten.

13. The transistor of claim 11 wherein the raised doped source and drain regions are made of epitaxial SiC.

14. The transistor of claim 12 wherein the raised doped source and drain regions are made of epitaxial SiGe.

15. A method of making a transistor, the method comprising:

doping an active area of a silicon substrate having a buried oxide layer therein, to form doped source and drain regions;

forming a planar epitaxial channel extending between the source and drain regions, the planar epitaxial channel at least partially recessed below an upper surface of an active region of the substrate;

forming a high-k gate dielectric in contact with the planar epitaxial channel;

forming a metal gate over the high-k gate dielectric, the metal gate surrounded on three sides by a metal barrier seed layer;

encapsulating the metal gate;

raising the doped source and drain regions by forming additional doped epitaxial layers in contact with the source and drain regions;

covering the transistor with an insulator; and

forming metal contacts to the metal gate and the source and drain regions.

16. The method of claim 15 further comprising forming isolation regions that separate N-type and P-type devices.

17. The method of claim 15 wherein the doping is carried out by ion implantation.

18. The method of claim 15 wherein the doping is carried out in-situ during a process of epitaxial growth.

19. The method of claim 15 wherein the transistor is a P-type device, and further comprising forming a work function material in contact with the metal barrier seed layer.

20. The method of claim 15 wherein the encapsulating covers at least three sides of the metal gate with silicon nitride.