ELECTROSTATIC PROTECTION CIRCUIT

• US 20150229125A1
• Filed: 09/02/2014
• Published: 08/13/2015
• Est. Priority Date: 02/10/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KATO, Kazuhiro, IKIMURA, Takehito
• Application Number:
  US14/475,520
• Publication Number:
  US 20150229125A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

According to one embodiment, an electrostatic protection circuit includes a first trigger circuit that is connected between a first power supply terminal and a second power supply terminal, and a second trigger circuit. The circuit includes a first buffer circuit that outputs a drive signal in response to a trigger signal of the first trigger circuit, and a second buffer circuit that outputs a drive signal in response to a trigger signal of the second trigger circuit. A shunt circuit includes a first switch circuit and a second switch circuit connected in series between the first and second power supply terminals. A conduction of the first switch circuit is controlled by a drive signal of the first buffer circuit, and a conduction of the second switch circuit is controlled by a drive signal of the second buffer circuit.

Claims

1. An electrostatic protection circuit, comprising:

a first trigger circuit connected between a first power supply terminal and a second power supply terminal and configured to output a first trigger signal;

a second trigger circuit connected between the first power supply terminal and the second power supply terminal, in parallel with the first trigger circuit, and configured to output a second trigger signal;

a first buffer circuit configured to output a first drive signal in response to the first trigger signal;

a second buffer circuit configured to output a second drive signal in response to the second trigger signal; and

a first switch circuit and a second switch circuit connected in series between the first and second power supply terminals,

wherein a conduction state of the first switch circuit is controlled by the first drive signal, and a conduction state of the second switch circuit is controlled by the second drive signal.

2. The electrostatic protection circuit according to claim 1, wherein when a predetermined power supply voltage is applied between the first and second power supply terminals, the first buffer circuit outputs a signal which turns the first switch circuit OFF, and the second buffer circuit outputs a signal which turns the second switch circuit ON.

3. The electrostatic protection circuit according to claim 1, wherein the first trigger circuit and the second trigger circuit each include a resistor and a capacitor connected in series, and a time constant of the first trigger circuit is larger than a time constant of the second trigger circuit.

4. The electrostatic protection circuit according to claim 1, further comprising:

a retaining unit that retains a level of the second trigger signal for a predetermined time.

5. The electrostatic protection circuit according to claim 4, wherein the second buffer circuit includes a first inverter, and

the retaining unit includes a second inverter that is connected in reverse-parallel to the first inverter.

6. The electrostatic protection circuit according to claim 4, wherein the retaining unit is reset by the first trigger signal.

7. The electrostatic protection circuit according to claim 1,

wherein the first switch circuit includes an NMOS transistor, a source of which is connected to the second power supply terminal, and

the second switch circuit includes a PMOS transistor, a source of which is connected to the first power supply terminal and a drain of which is connected to a drain of the NMOS transistor.

8. The electrostatic protection circuit according to claim 1, wherein at least one the first and second switches is a bipolar transistor.

9. The electrostatic protection circuit according to claim 1, wherein at least one of the first and second switches is a metal-oxide-semiconductor field effect transistor.

10. The electrostatic protection circuit according to claim 1, wherein the first buffer circuit comprises a plurality of CMOS inverters connected in series.

11. The electrostatic protection circuit according to claim 1, wherein

the first switch includes an NMOS transistor having a source electrode and a back gate electrode each connected to the second power supply terminal and a gate electrode connected to the first buffer circuit, and

the second switch includes a PMOS transistor having a source electrode and a back gate electrode each connected to the first power supply terminal, a gate electrode connected to the second buffer circuit, and a drain electrode connected to a drain electrode of the NMOS transistor included in the first switch.

12. An electrostatic protection circuit, comprising:

a first switch and second switch connected in series between two nodes;

a first trigger circuit and second trigger circuit configured to control, respectively, the first switch and the second switch to provide a closed circuit path between the two nodes upon occurrence of an ESD event and to maintain an open circuit path otherwise.

13. The electrostatic protection circuit according to claim 12, wherein

the first trigger circuit has a first time constant and the second trigger circuit has a second time constant,

the first time constant corresponding to an expected voltage rise caused by an ESD event,

the second time constant being less than the first time constant.

14. The electrostatic protection circuit according to claim 12, wherein

the first switch is normally OFF and the second switch is normally ON, and

the first trigger circuit closes the first switch when the ESD event occurs.

15. The electrostatic protection circuit according to claim 12, wherein

the first switch is normally OFF and the second switch is normally ON, and

the second trigger circuit opens the second switch when a power supply voltage variation event other than the ESD event occurs.

16. The electrostatic protection circuit according to claim 12, wherein

the first switch is normally OFF and the second switch is normally ON, and

the second trigger circuit opens the second switch for a predetermined time after a power supply voltage variation event other than the ESD event occurs.

17. The electrostatic protection circuit according to claim 12, further comprising:

a first buffer circuit between the first trigger circuit and the first switch; and

a second buffer circuit between the second trigger circuit and the second switch.

18. A method for protecting a circuit, the method comprising:

generating a first trigger signal according to a first time constant;

generating a second trigger signal according to a second time constant, the second time constant being shorter than the first time constant; and

closing a circuit path based on the first trigger and the second trigger when the duration of an event is about the same time as the first time constant; and

maintaining the circuit path in open state otherwise.

19. The method according to claim 18, wherein the first time constant is set to correspond to the duration of an ESD event.

20. The method according to claim 18, wherein the second time constant is set to correspond to the duration of a power supply voltage variation corresponding to power supply startup.