CLOCK CONTROL CIRCUIT, RECEIVER, AND COMMUNICATION DEVICE

• US 20150229298A1
• Filed: 01/13/2015
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: TOMITA, Yasumoto, Mori, Toshihiko
• Granted Patent: US 9,281,805 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Claims

1. A clock control circuit comprising:

a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks;

a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and

a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

2. The clock control circuit according to claim 1,

wherein the multi-phase clocks are four-phase clocks, phases of which are different from each other by 90°

, and

wherein the first pair of input clocks and the second pair of input clocks are respective complementary clocks, phases of which are different from each other by 180°

.

3. The clock control circuit according to claim 1,

wherein the frequency multiplier includes a logic circuit that performs an exclusive OR operation on the output of the first buffer and the output of the second buffer.

4. The clock control circuit according to claim 1,

wherein the second buffer includes a first operation mode that buffers and outputs the second pair of input clocks, and a second operation mode that outputs a high level and a low level of the fixed level.

5. The clock control circuit according to claim 4,

wherein the first operation mode is an operation mode at the time of normal operation in which the first and second buffers buffer and output the first pair of input clocks and second pair of input clocks, and

wherein the second operation mode is an operation mode at the time of power-down in which the second buffer outputs the fixed level regardless of a level of the second pair of input clocks.

6. A clock control circuit comprising:

a phase shift circuit that receives first multi-phase clocks and outputs second multi-phase clocks which are obtained by phase-shifting a predetermined clock;

a first buffer that receives a first pair of input clocks of the second multi-phase clocks, and buffers and outputs the first pair of input clocks;

a second buffer that receives a second pair of input clocks of the second multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level;

a first frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clock, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the first multi-phase clocks;

a third buffer that receives a third pair of input clocks of the second multi-phase clocks, and buffers and outputs the third pair of input clocks;

a fourth buffer that receives a fourth pair of input clocks of the second multi-phase clocks, and is controllable to buffer and output the fourth pair of input clocks or to output a fixed level; and

a second frequency multiplier that performs a logical operation on an output of the third buffer and an output of the fourth buffer, and outputs a third pair of output clocks or a fourth pair of output clocks as an output clock, the third pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and the fourth pair of output clocks is based on the same frequencies as the first multi-phase clocks.

7. The clock control circuit according to claim 6,

wherein the first multi-phase clocks are eight-phase clocks, phases of which are different from each other by 45°

, and

wherein the first pair of input clocks, the second pair of input clocks, the third pair of input clocks, and the fourth pair of input clocks are respective complementary clocks, phases of which are different from each other by 180°

.

8. The clock control circuit according to claim 6,

wherein the first frequency multiplier includes a circuit that performs an exclusive OR operation on an output of the first buffer and an output of the second buffer, and

wherein the second frequency multiplier includes a circuit that performs an exclusive OR operation on an output of the third buffer and an output of the fourth buffer.

9. The clock control circuit according to claim 6,

wherein the second and fourth buffers include a first operation mode that buffers and outputs the second pair of input clocks and fourth pair of input clocks, and a second operation mode that outputs a high level and a low level of the fixed level.

10. The clock control circuit according to claim 9,

wherein the first operation mode is an operation mode at the time of normal operation in which the first to fourth buffers buffer and output the first to fourth pair of input clocks, and

wherein the second operation mode is an operation mode at the time of power-down in which the second and fourth buffers output the fixed level regardless of levels of the second and fourth clock pairs.

11. The clock control circuit according to claim 9,

wherein the phase shift circuit includes a switch that switches a predetermined clock of the first multi-phase clocks in the second operation mode.

12. The clock control circuit according to claim 9,

wherein in the second operation mode, the phase shift circuit includes a code adder that adds a predetermined code to a phase code with respect to a phase interpolator, and shifts a phase of a predetermined clock of the first multi-phase clocks.

13. A receiver comprising:

a clock control circuit including

a phase shift circuit that receives first multi-phase clocks and outputs second multi-phase clocks which are obtained by phase-shifting a predetermined clock,

a first buffer that receives a first pair of input clocks of the second multi-phase clocks, buffers and outputs the first pair of input clocks,

a second buffer that receives a second pair of input clocks of the second multi-phase clocks, and is controllable to buffer and input the second pair of input clocks or to output a fixed level,

a first frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clock, first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the first multi-phase clocks,

a third buffer that receives a third pair of input clocks of the second multi-phase clocks, buffers and outputs the third pair of input clocks,

a fourth buffer that receives a fourth pair of input clocks of the second multi-phase clocks, and is controllable to buffer and output the fourth pair of input clocks or to output a fixed level, and

a second frequency multiplier that performs a logical operation of an output of the third buffer and an output of the fourth buffer, and outputs a third pair of output clocks or a fourth pair of output clocks as an output clock, the third pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and a fourth pair of output clocks is based on the same frequencies as the first multi-phase clocks;

a data determination circuit that determines data based on a first output clock from the clock control circuit;

a boundary determination circuit that determines a boundary based on a second output clock from the clock control circuit; and

a clock data recovery that controls a phase interpolator based on outputs of the data determination circuit and the boundary determination circuit.

14. A communication device comprising:

a receiver receives an input signal from an external device;

a signal processing circuit processes the input signal that is input via the receiver; and

a transmitter output an output signal that is processed by the signal processing circuit to the external device,

wherein the receiver comprising;

a clock control circuit including

a phase shift circuit that receives first multi-phase clocks and outputs second multi-phase clocks which are obtained by phase-shifting a predetermined clock,

a first buffer that receives a first pair of input clocks of the second multi-phase clocks, buffers and outputs the first pair of input clocks, a second buffer that receives a second pair of input clocks of the second multi-phase clocks, and is controllable to buffer and input the second pair of input clocks or to output a fixed level,

a first frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clock, first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the first multi-phase clocks,

a third buffer that receives a third pair of input clocks of the second multi-phase clocks, buffers and outputs the third pair of input clocks,

a fourth buffer that receives a fourth pair of input clocks of the second multi-phase clocks, and is controllable to buffer and output the fourth pair of input clocks or to output a fixed level, and

a second frequency multiplier that performs a logical operation of an output of the third buffer and an output of the fourth buffer, and outputs a third pair of output clocks or a fourth pair of output clocks as an output clock, the third pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the first multi-phase clocks, and a fourth pair of output clocks is based on the same frequencies as the first multi-phase clocks;

a data determination circuit that determines data based on a first output clock from the clock control circuit;

a boundary determination circuit that determines a boundary based on a second output clock from the clock control circuit; and

a clock data recovery that controls a phase interpolator based on outputs of the data determination circuit and the boundary determination circuit.