SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

• US 20150229309A1
• Filed: 02/03/2015
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 9,479,175 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A semiconductor in which the area of a circuit that is unnecessary during normal operation is small is provided. A semiconductor device including a first circuit has a function of storing a start-up routine in the first circuit and executing the start-up routine, a function of operating the first circuit as a buffer memory device after executing the start-up routine, and a function of loading the start-up routine into the first circuit from outside before the semiconductor device is powered off.

Claims

1. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of storing a start-up routine in the memory circuit and executing the start-up routine,

wherein the semiconductor device is capable of operating the memory circuit as a buffer memory device after executing the start-up routine,

wherein the semiconductor device is capable of loading the start-up routine into the memory circuit from outside after operating the memory circuit as the buffer memory device and before powering off the semiconductor device,

wherein the memory circuit comprises a first transistor, a second transistor, a first circuit, and a second circuit,

wherein the first transistor and the second transistor are electrically connected to each other in series,

wherein a gate of the first transistor is electrically connected to an output terminal of the first circuit,

wherein the gate of the first transistor is electrically connected to an input terminal of the second circuit,

wherein an input terminal of the first circuit is electrically connected to an output terminal of the second circuit,

wherein the first circuit comprises a third transistor and a fourth transistor,

wherein the second circuit comprises a fifth transistor and a sixth transistor,

wherein the first transistor, the second transistor, the third transistor, and the fifth transistor have a first polarity, and

wherein the fourth transistor and the sixth transistor have a second polarity.

2. The semiconductor device according to claim 1,

wherein the semiconductor device is capable of measuring a length of a period in which a supply of power to the semiconductor device is stopped, and

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after the supply of power,

wherein the semiconductor device is capable of executing the start-up routine after loading the start-up routine into the memory circuit from outside when the period is longer than the preset period, and

wherein the semiconductor device is capable of executing the start-up routine stored in the memory circuit before the semiconductor device is powered off when the period is shorter than the preset period.

3. The semiconductor device according to claim 1,

wherein a channel portion of the first transistor, a channel portion of the second transistor, a channel portion of the third transistor, and a channel portion of the fifth transistor contain a first semiconductor material,

wherein a channel portion of the fourth transistor and a channel portion of the sixth transistor contain a second semiconductor material, and

wherein the second semiconductor material comprises an oxide semiconductor.

4. An electronic device comprising:

the semiconductor device according to claim 1; and

a housing, a display device, a microphone, or a speaker.

5. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of performing a first operation and performing a second operation,

wherein the semiconductor device is capable of being powered off between the first operation and the second operation,

wherein the semiconductor device is capable of storing a start-up routine of the semiconductor device in the memory circuit before the first operation,

wherein the semiconductor device is capable of executing the start-up routine in the first operation,

wherein the semiconductor device is capable of performing an operation based on a setting according to a data stored in the memory circuit in the second operation,

wherein the memory circuit comprises a first transistor, a second transistor, a first circuit, and a second circuit,

wherein the first transistor and the second transistor are electrically connected to each other in series,

wherein a gate of the first transistor is electrically connected to an output terminal of the first circuit,

wherein the gate of the first transistor is electrically connected to an input terminal of the second circuit,

wherein an input terminal of the first circuit is electrically connected to an output terminal of the second circuit,

wherein the first circuit comprises a third transistor and a fourth transistor,

wherein the second circuit comprises a fifth transistor and a sixth transistor,

wherein the first transistor, the second transistor, the third transistor, and the fifth transistor have a first polarity, and

wherein the fourth transistor and the sixth transistor have a second polarity.

6. The semiconductor device according to claim 5,

wherein the semiconductor device is capable of measuring a length of a period in which the semiconductor device is powered off,

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after a supply of power,

wherein the semiconductor device is capable of executing the start-up routine after loading the start-up routine into the memory circuit from outside when the period is longer than the preset period, and

wherein the semiconductor device is capable of executing the start-up routine stored in the memory circuit before the semiconductor device is powered off when the period is shorter than the preset period.

7. The semiconductor device according to claim 5,

wherein the memory circuit operates as a buffer memory device in the second operation.

8. The semiconductor device according to claim 5, further comprising:

a logic circuit,

wherein the logic circuit comprises a plurality of third circuits, and

wherein the memory circuit is capable of controlling electrical connection between the plurality of third circuits according to the data.

9. The semiconductor device according to claim 5,

wherein a channel portion of the first transistor, a channel portion of the second transistor, a channel portion of the third transistor, and a channel portion of the fifth transistor contain a first semiconductor material,

wherein a channel portion of the fourth transistor and a channel portion of the sixth transistor contain a second semiconductor material, and

wherein the second semiconductor material comprises an oxide semiconductor.

10. An electronic device comprising:

the semiconductor device according to claim 5; and

a housing, a display device, a microphone, or a speaker.

11. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of performing a first operation, being powered off, and then performing a second operation,

wherein the semiconductor device is capable of performing an operation based on a first setting according to a data stored in the memory circuit in the first operation,

wherein the semiconductor device is capable of storing a second setting of the semiconductor device in the memory circuit before the semiconductor device is powered off,

wherein the semiconductor device is capable of executing a program for the second setting of the semiconductor device in the second operation,

wherein the memory circuit comprises a first transistor, a second transistor, a first circuit, and a second circuit,

wherein the first transistor and the second transistor are electrically connected to each other in series,

wherein a gate of the first transistor is electrically connected to an output terminal of the first circuit,

wherein the gate of the first transistor is electrically connected to an input terminal of the second circuit,

wherein an input terminal of the first circuit is electrically connected to an output terminal of the second circuit,

wherein the first circuit comprises a third transistor and a fourth transistor,

wherein the second circuit comprises a fifth transistor and a sixth transistor, and

wherein the first transistor, the second transistor, the third transistor, and the fifth transistor have a first polarity.

12. The semiconductor device according to claim 11,

wherein the semiconductor device is capable of measuring a length of a period in which the semiconductor device is powered off,

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after a supply of power, and

wherein the semiconductor device is capable of executing the program for the second setting of the semiconductor device when the period is shorter than the preset period.

13. The semiconductor device according to claim 11,

wherein the memory circuit operates as a buffer memory device in the first operation.

14. The semiconductor device according to claim 11, further comprising:

a logic circuit,

wherein the logic circuit comprises a plurality of third circuits, and

wherein the memory circuit is capable of controlling electrical connection between the plurality of third circuits according to the data.

15. The semiconductor device according to claim 11,

wherein a channel portion of the first transistor, a channel portion of the second transistor, a channel portion of the third transistor, and a channel portion of the fifth transistor contain a first semiconductor material,

wherein a channel portion of the fourth transistor and a channel portion of the sixth transistor contain a second semiconductor material, and

wherein the second semiconductor material comprises an oxide semiconductor.

16. An electronic device comprising:

the semiconductor device according to claim 11; and

a housing, a display device, a microphone, or a speaker.