MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING

• US 20150229337A1
• Filed: 02/28/2014
• Published: 08/13/2015
• Est. Priority Date: 02/11/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Alhussien, AbdelHakim S., Djurdjevic, Ivana, Cai, Yu, Haratsch, Erich F., Li, Yue, Cohen, Earl T.
• Granted Patent: US 9,319,073 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics

Abstract

An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Claims

1. An apparatus comprising:

a controller configured to read data from and write data to multi-level cell flash memory; and

an adaptive strength error correction code (ECC) decoder, wherein said controller is further configured to write data in a two-step process comprising (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process, and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

2. The apparatus according to claim 1, wherein said first strength is lower than said second strength.

3. The apparatus according to claim 1, wherein writing data to said MSB page is separated in time from writing data to said LSB page.

4. The apparatus according to claim 1, wherein said adaptive error correction code decoder is configured to switch between said first strength and said second strength.

5. The apparatus according to claim 1, further comprising a memory device comprising multi-level cell flash memory.

6. The apparatus according to claim 5, wherein said memory device, said controller, and said ECC decoder are implemented as one or more integrated circuits.

7. The apparatus according to claim 5, wherein said memory device, said controller, and said ECC decoder are part of a solid state disk or drive.

8. The apparatus according to claim 1, wherein said controller is further configured to store metadata indicating a result of reading said LSB page with said first strength ECC decoding process.

9. The apparatus according to claim 8, wherein said metadata is stored in at least one of said controller and a memory device connected to said controller.

10. The apparatus according to claim 8, wherein said controller is configured to adjust a writing process for said MSB page based upon the stored metadata indicating a result of reading said LSB page with said first strength ECC decoding process.

11. The apparatus according to claim 8, wherein said controller is configured to write data to said MSB page that can assist decoding said LSB page based upon the stored metadata.

12. The apparatus according to claim 8, wherein said controller is configured to adjust a decoding process performed on said LSB and MSB pages based upon the stored metadata.

13. A method of writing data to a memory device comprising multi-level cell flash memory, said method comprising:

writing data to a least significant bit (LSB) page;

after writing data to said LSB page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process;

writing data to a most significant bit (MSB) page associated with the LSB page; and

after writing data to said MSB page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

14. The method according to claim 13, wherein the LSB and MSB pages have a common wordline.

15. The method according to claim 13, wherein said first strength is lower than said second strength.

16. The method according to claim 13, wherein the step of writing data to said MSB page is separated in time from the step of writing data to said LSB page.

17. The method according to claim 13, further comprising:

storing metadata indicating a result of reading said LSB page with said first strength ECC decoding process.

18. The method according to claim 17, further comprising:

adjusting a writing process for said MSB page based upon the stored metadata indicating a result of reading said LSB page with said first strength ECC decoding process.

19. The method according to claim 17, further comprising:

writing data to said MSB page that can assist decoding said LSB page based upon the stored metadata.

20. The method according to claim 17, further comprising:

adjusting a decoding process performed on said LSB and MSB pages based upon the stored metadata.