LOW POWER PROPORTIONAL TO ABSOLUTE TEMPERATURE CURRENT AND VOLTAGE GENERATOR

• US 20150234414A1
• Filed: 02/18/2014
• Published: 08/20/2015
• Est. Priority Date: 02/18/2014
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Technology (Analog Devices, Inc.)
• Inventors: Marinca, Stefan
• Granted Patent: US 9,658,637 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A proportional to absolute temperature (PTAT) circuit is provided. By judiciously combining circuit elements into two or more cell it is possible to effectively dump bias current into impedance resistive element of a first cell from other cells of the circuit. As a result the circuit as a whole can operate with smaller resistive elements and therefore occupy less area when implemented in silicon. It is also possible to reduce the supply current that is required for providing specific output currents or voltages.

Claims

1. A proportional to absolute temperature (PTAT) circuit, the circuit comprising:

a first set of circuit components comprising a first bipolar transistor operating at a first collector current density and a second bipolar transistor operating at a second, lower, collector current density, the first and second bipolar transistors configured to provide a first voltage component related to a base-emitter voltage difference, the first set of circuit components further comprising a resistive load element and configured to generate a first bias current of the circuit having a value related to a value of the resistive load element and the first voltage component; and

a second set of circuit components coupled to the first set of circuit components and operably biased by a voltage originating within the first set of circuit components and providing a second bias current into the first set of circuit components.

2. The circuit of claim 1, wherein the second set of circuit components is configured to generate at least a second voltage component related to a base-emitter voltage difference.

3. The circuit of claim 2, wherein the at least a second voltage component related to a base-emitter voltage difference is generated from an emitter ratio of a third bipolar transistor operating at a first collector current density and a fourth bipolar transistor operating at a second, lower, collector current density.

4. The circuit of claim 2, wherein the circuit is configured to combine the first and at least a second voltage component to provide at an output of the circuit a PTAT voltage that is dependent on the base emitter voltage difference between first and second sets of bipolar transistors operating at different current densities.

5. The circuit of claim 1, wherein the second bias current is coupled into the first set of circuit components at a node where the first bias current is generated.

6. The circuit of claim 3, further comprising:

a third set of circuit components configured to generate a third voltage component related to a base-emitter voltage difference generated from an emitter ratio of a fifth bipolar transistor operating at a first collector current density and a sixth bipolar transistor operating at a second, lower, collector current density;

wherein the third set of circuit components is coupled to the second set of circuit components and is operably biased by a voltage originating within the first set of circuit components.

7. The circuit of claim 6, wherein the third set of circuit components is configured to provide a bias current into the first set of circuit components.

8. The circuit of claim 4, further comprising a resistor across which the PTAT voltage is replicated to generate a PTAT current.

9. The circuit of claim 4, further comprising a MOS device operating in a triode region across which the PTAT voltage is replicated to generate a PTAT current.

10. The circuit of claim 4, further comprising a voltage buffer configured to buffer the PTAT voltage and provide a bias current into the first set of circuit elements.

11. The circuit of claim 4, further comprising:

a circuit element configured to generate a complimentary to absolute temperature (CTAT) voltage component,

wherein the circuit is configured to couple the CTAT voltage component to the PTAT voltage to provide, at an output of the circuit, an output voltage that is first order temperature insensitive.

12. The circuit of claim 11, wherein the CTAT voltage component comprises a bipolar transistor providing a base emitter voltage which is coupled to the PTAT voltage.

13. The circuit of claim 11, wherein CTAT voltage component is provided by a plurality of diode connected transistors coupled to a bipolar transistor, the diode connected transistors effecting a division of a base-emitter voltage originating from the bipolar transistor into three voltage components.

14. The circuit of claim 13, further comprising a resistor string configured to allow an adjustment of the output voltage.

15. A proportional to absolute temperature (PTAT) circuit configured to generate a voltage at an output node of the circuit that is temperature dependent, the circuit comprising:

a plurality of circuit elements coupled to a single biasing current,

a first set of circuit elements configured to operate as a bias current generator and as a first PTAT voltage cell of the circuit; and

a second set of circuit elements biased from the first set of circuit elements and configured to return at least one bias current to a common node within the first set of circuit elements.

16. The circuit of claim 15, wherein the second set of circuit elements is configured to provide at least one cell providing a second PTAT cell of the circuit.

17. The circuit of claim 16, wherein the second set of circuit elements are arranged in at least two individual cells, each individual cell configured to generate a PTAT voltage.

18. The circuit of claim 17, wherein an output PTAT voltage of the circuit is a compound voltage generated by combining individual PTAT voltages from each individual cell.

19. The circuit of claim 18, further comprising a circuit element configured to generate a complimentary to absolute temperature (CTAT) voltage component, the circuit being configured to couple the CTAT voltage component to the output PTAT voltage to provide, at an output of the circuit, an output voltage that is first order temperature insensitive.

20. The circuit of claim 19, wherein the CTAT voltage component comprises a bipolar transistor providing a base emitter voltage which is coupled to the output PTAT voltage.

21. The circuit of claim 19, wherein the CTAT voltage component is provided by a plurality of diode connected transistors coupled to a bipolar transistor, the diode connected transistors effecting a division of a base-emitter voltage originating from the bipolar transistor into three voltage components.

22. The circuit of claim 21, further comprising a resistor string configured to allow an adjustment of the output voltage.

23. A method of generating a proportional to absolute temperature (PTAT) voltage, the method comprising:

providing a plurality of circuit elements coupled to a single biasing current;

configuring a first set of circuit elements to operate as a bias current generator and as a first PTAT voltage cell of the circuit; and

providing a second set of circuit elements biased from the first set of circuit elements and configured to return at least one bias current to a common node within the first set of circuit elements.

24. The method of claim 23, further comprising:

configuring the second set of circuit elements to provide at least one cell providing a second PTAT cell of the circuit; and

combining PTAT voltages from the first and second PTAT cells of the circuit at an output of the circuit to generate a PTAT voltage.

25. The method of claim 24, further comprising coupling the PTAT voltage to a voltage having a complimentary to absolute temperature (CTAT) form to generate at an output of the circuit a voltage that is first order temperature insensitive.

26. The method of claim 24, further comprising generating a PTAT current by replicating the PTAT voltage across a resistive load.

27. The method of claim 24, further comprising providing a voltage buffer at the output of the circuit to buffer the PTAT voltage.

28. The method of claim 25, further comprising providing a voltage divider configured to divide down the voltage having a complimentary to absolute temperature (CTAT) form.