CACHE MEMORY CONTROLLER AND CACHE MEMORY CONTROL METHOD

• US 20150234747A1
• Filed: 04/16/2013
• Published: 08/20/2015
• Est. Priority Date: 08/22/2012
• Status: Abandoned Application

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kijima, Junko, Naito, Masahiro, Tanaka, Saori
• Application Number:
  US14/411,709
• Publication Number:
  US 20150234747A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions

Abstract

A cache memory controller (100) connected to a main memory (10) having an instruction area storing a first program and a data area storing data used by a specific instruction included in the first program, and to an access master (1) for executing instructions included in the first program. The cache memory controller is provided with a cache memory (110) for storing a portion of the data in the main memory (10), and a data processing unit (140) that, prior to execution of the specific instruction by the access master (1), and in accordance with transfer scheduling information including the starting address of the specific instruction, calculates an access interval on a basis of the number of instruction steps remaining from the address of the instruction currently being executed by the access master (1) to the starting address of the specific instruction, and transfers data used by the specific instruction from the main memory (10) to the cache memory (110) at this access interval.

Claims

1-36. -36. (canceled)

37. A cache memory controller connected to a main memory having an instruction area storing a first program and a data area storing data used by a specific instruction included in the first program, and to an access master for executing instructions included in the first program, the cache memory controller comprising:

a cache memory for storing a portion of the data in the main memory; and

a data processing unit that, prior to execution of the specific instruction by the access master, in accordance with transfer scheduling information including a starting address of the specific instruction and size of the data used by the specific instruction, calculates an access interval representing a number of remaining instruction steps for each unit of transfer on a basis of a number of instruction steps remaining from an address of an instruction currently being executed by the access master to the starting address of the specific instruction and, in the size of the data used by the specific instruction, remaining size of data that have not been transferred to the cache memory yet, and transfers data used by the specific instruction from the main memory to the cache memory at the calculated access interval.

38. A cache memory controller connected to a main memory having an instruction area storing a first program and a data area storing data used by a specific instruction included in the first program, and to an access master for executing instructions included in the first program, the cache memory controller comprising:

a cache memory for storing a portion of the data in the main memory; and

a data processing unit that, prior to execution of the specific instruction by the access master, and in accordance with transfer scheduling information including a starting address of the specific instruction, calculates an access interval on a basis of a number of instruction steps remaining from an address of an instruction currently being executed by the access master to the starting address of the specific instruction, and, when a plurality of items of the transfer scheduling information are processed, determines an item of transfer scheduling information of highest priority, and transfers data used by the specific instruction from the main memory to the cache memory at the access interval of the item of the transfer scheduling information of highest priority.

39. The cache memory controller of claim 38, wherein the data processing unit determines the item of transfer scheduling information of highest priority on a basis of the access interval.

40. The cache memory controller of claim 38, wherein the data processing unit receives the plurality of items of the transfer scheduling information from the access master, and determines the item of transfer scheduling information of highest priority on a basis of the access interval and a time since last access, the time since last access being a time that elapses without access from the access master to each of a predetermined plurality of continuous areas in the main memory.

41. The cache memory controller of claim 38, wherein

the data processing unit compares the access intervals calculated for the plurality of items of the transfer scheduling information received from the access master with a preset first threshold value;

when the calculated access intervals are equal to or less than the preset first threshold value, the data processing unit determines the item of transfer scheduling information of highest priority on a basis of a starting address of an instruction group that refers to a continuous area in which data to be transferred are stored,

when the calculated access intervals are greater than the preset first threshold value, the data processing unit does not determine an item of transfer scheduling information of highest priority, but defers processing until access intervals recalculated for the plurality of items of the transfer scheduling information received from the access master are equal to or less than the preset first threshold value.

42. A cache memory control method for using a cache memory to provide an access master that executes instructions included in a first program with data used by a specific instruction in the first program from a main memory having an instruction area for storing the first program and a data area for storing the data used by the specific instruction, the cache memory control method comprising:

a transfer step for, prior to execution of the specific instruction by the access master, and in accordance with transfer scheduling information including a starting address of the specific instruction, calculating an access interval on a basis of a number of instruction steps remaining from an address of an instruction currently being executed by the access master to the starting address of the specific instruction, and transferring the data used by the specific instruction, and, when a plurality of items of the transfer scheduling information are processed, determining an item of transfer scheduling information of highest priority; and

a providing step for providing the data used by the specific instruction from the cache memory to the access master when the access master executes the specific instruction.