Through Via Structure Extending to Metallization Layer

• US 20150235922A1
• Filed: 05/22/2014
• Published: 08/20/2015
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yi-Hsiu, Yang, Ku-Feng, Chiou, Wen-Chih, Jeng, Shin-Puu, Yu, Chen-Hua
• Granted Patent: US 10,170,396 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The integrated circuit device disclosed herein includes a substrate, an interlevel dielectric layer disposed over the substrate, an intermetal dielectric layer disposed over the interlevel dielectric layer, an interconnect structure extending through the intermetal dielectric layer, and a through via (TV) extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the interconnect structure. In some embodiments, the through via is formed before the interconnect structure. In other embodiments, the interconnect structure is formed before the through via. In an embodiment, a fin field effect transistor (FinFET) is formed over the substrate.

Claims

1. A device, comprising:

a substrate;

an interlevel dielectric layer disposed over the substrate;

an intermetal dielectric layer disposed over the interlevel dielectric layer;

an interconnect structure extending through the intermetal dielectric layer; and

a through via (TV) extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the interconnect structure.

2. The device of claim 1, wherein the interconnect structure is a dual-damascene structure including a conductive via underlying a conductive line.

3. The device of claim 2, wherein the conductive line is formed in a first metallization one layer (M1).

4. The device of claim 1, wherein an etch stop layer is disposed over the top surface of the interconnect structure and the top surface of the through via.

5. The device of claim 1, wherein the interconnect structure is electrically coupled to a metal contact extending through the interlevel dielectric layer, the interlevel dielectric layer interposed between the intermetal dielectric layer and the substrate.

6. The device of claim 1, wherein the interconnect structure and the through via are formed from a same material.

7. The device of claim 1, wherein the interconnect structure is a first dual-damascene structure electrically coupled to a second dual-damascene structure.

8. The device of claim 1, wherein the through via is electrically coupled to a dual-damascene structure.

9. The device of claim 1, wherein the interconnect structure is vertically disposed over and electrically coupled to a gate of a fin field effect transistor (FinFET).

10. The device of claim 9, wherein a metal contact is disposed between the interconnect structure and the gate of the FinFET.

11. A device, comprising:

a substrate;

a fin field effect transistor (FinFET) disposed over the substrate;

one or more interlevel dielectric layers disposed over the FinFET;

an intermetal dielectric layer disposed over the one or more interlevel dielectric layers;

a contact electrically coupled to a gate of the FinFET and extending through at least one of the one or more interlevel dielectric layers;

an interconnect structure extending through the intermetal dielectric layer, the interconnect structure electrically coupled to the contact; and

a through via (TV) extending through the one or more interlevel dielectric layers and the intermetal dielectric layer, the through via having a top surface co-planar with a top surface of the interconnect structure.

12. The device of claim 11, wherein the interconnect structure comprises a dual-damascene structure.

13. The device of claim 11, wherein an etch stop layer is disposed over each of the one or more interlevel dielectric layers.

14. The device of claim 11, wherein the interconnect structure is a first dual-damascene structure electrically coupled to a second dual-damascene structure.

15. The device of claim 11, wherein the interconnect structure is in a metal one layer (M1).

16. The device of claim 11, wherein the contact comprises tungsten and the interconnect structure comprises copper.

17. A method of forming an integrated circuit, comprising:

forming a metal via and a metal line in an intermetal dielectric layer disposed over a substrate using a dual-damascene process, the metal line formed in a metal one layer (M1); and

forming a through via (TV) extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the metal line.

18. The method of claim 17, further comprising protecting the intermetal dielectric layer with at least one of a stop layer and a cap layer during formation of the through via.

19. The method of claim 17, wherein the forming the through via is performed prior to the forming the metal via and the metal line.

20. The method of claim 17, further comprising forming a fin field effect transistor (FinFET) over the substrate, a gate of the fin field effect transistor electrically coupled to the metal via.