SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME

• US 20150235989A1
• Filed: 08/29/2014
• Published: 08/20/2015
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Lii, Mirng-Ji, Lee, Chien-Hsun, Wang, Tsung-Ding, Cheng, Jung Wei, Hou, Hao-Cheng, Lin, Hung-Jen, Liu, Ming-Che
• Granted Patent: US 10,026,671 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/11903 using different masks
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/9222 : Sequential connecting processes
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

Claims

1. A device package comprising:

a first die;

one or more redistribution layers (RDLs) electrically connected to the first die, wherein the one or more RDLs extend laterally past edges of the first die;

one or more second dies bonded to a first surface of the one or more RDLs;

a connector element on the first surface of the one or more RDLs, wherein the connector element has a vertical dimension greater than the one or more second dies; and

a package substrate bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

2. The device package of claim 1, wherein the connector element comprises:

a first conductive pillar on the first surface of the one or more RDLs; and

a solder region disposed on the first conductive pillar.

3. The device package of claim 2, wherein the connector element further comprises a second conductive pillar on a second surface of the package substrate, wherein the solder region is disposed between the first conductive pillar and the second conductive pillar.

4. The device package of claim 2, wherein the first conductive pillar has a greater vertical dimension than the solder region.

5. The device package of claim 1, wherein the connector element comprises:

a solder region;

a molded underfill surrounding the solder region; and

a solder ball on the solder region.

6. The device package of claim 5, wherein the molded underfill further extends at least partially along sidewalls of the one or more second dies.

7. The device package of claim 1, wherein the connector element is an interposer comprising a through hole, wherein the one or more second dies are at least partially disposed in the through hole.

8. The device package of claim 7, wherein the interposer further comprises a substrate and a copper via extending through the substrate.

9. The device package of claim 7, wherein the interposer comprises a substrate and a solder region extending through the substrate.

10. A device package comprising:

a first die;

a molding compound extending along sidewalls of the first die;

one or more redistribution layers (RDLs) on the first die and the molding compound;

a plurality of second dies bonded to a surface of the one or more RDLs opposing the first die and the molding compound;

a connector element on the surface of the one or more RDLs, wherein the connector element bonds a package substrate to the one or more RDLs, and wherein the plurality of second dies is disposed between the one or more RDLs and the package substrate; and

a heat dissipation feature on an opposing surface of the first die as the one or more RDLs.

11. The device package of claim 10, wherein the connector element has a first vertical dimension greater than a second vertical dimension of the plurality of second dies.

12. The device package of claim 10, wherein the connector element comprises a conductive pillar and a solder region on the conductive pillar.

13. The device package of claim 10, wherein the connector element comprises an interposer, wherein the interposer comprises a through hole, and wherein the plurality of second dies is at least partially disposed in the through hole.

14. The device package of claim 13, wherein the interposer further comprises a conductive via extending through the interposer, and wherein the conductive via electrically connects the package substrate to the one or more RDLs.

15. A method for forming a device package comprising:

forming one or more redistribution layers (RDLs) on a first die, wherein the one or more RDLs extend laterally past edges of the first die;

bonding one or more second dies to a surface of the one or more RDLs opposing the first die;

forming a connector element on the surface of the one or more RDLs, wherein the connector element has a first vertical dimension greater than a second vertical dimension of the one or more second dies; and

bonding a package substrate to the surface of the one or more RDLs using the connector element, wherein the one or more second dies are disposed between the one or more RDLs and the package substrate.

16. The method of claim 15, wherein forming the connector element comprises:

forming a first conductive pillar on the surface of the one or more RDLs; and

forming a first solder region on the first conductive pillar.

17. The method of claim 16, wherein forming the connector element further comprises:

forming a second conductive pillar on the package substrate; and

bonding the first solder region to the second conductive pillar.

18. The method of claim 16, wherein forming the connector element further comprises:

forming a molded underfill extending along sidewalls of the first solder region;

planarizing an exposed surface of first solder region; and

forming a second solder region on the exposed surface of the first solder region.

19. The method of claim 15, wherein forming the connector element comprises bonding an interposer to the surface of the one or more RDLs, wherein the interposer comprises a first through hole, and wherein bonding the interposer comprises disposing the one or more second dies at least partially in the first through hole.

20. The method of claim 19, wherein the interposer further comprises a second through hole, and wherein bonding the interposer further comprises disposing a solder region through the second through hole.