Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices

• US 20150236023A1
• Filed: 04/29/2015
• Published: 08/20/2015
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wang, Kuo Chen, Manavalan, Sriraj, Liao, Wei Ming
• Granted Patent: US 9,287,271 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Claims

1-29. -29. (canceled)

30. A method of forming a plurality of vertical transistor devices;

individual devices comprising an outer source/drain region, an inner source/drain region, and a channel region each formed within an active area;

a plurality of gate line pairs on opposing sides of multiple channel regions;

a plurality of buried data/sense lines angling beneath the gate line pairs;

the inner source/drain regions individual electrically coupling to individual buried data/sense lines, the method comprising;

forming lines of active area alternating with lines of dielectric isolation within a semiconductor substrate;

etching buried data/sense line trenches into the lines of active area and lines of dielectric isolation, the buried data/sense line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation, individual lines of dielectric isolation underlying multiple buried data/sense line trenches;

forming the data/sense lines within the buried data/sense line trenches;

etching gate line trenches into the semiconductor substrate, the gate line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation and bifurcating the active area between two immediately adjacent data/sense lines;

forming the conductive gate line pairs within the gate line trenches; and

forming the outer and inner source/drain regions and the channel regions within the active area.

31. The method of claim 30 comprising forming a doped isolation region within the lines of active area between immediately adjacent buried data/sense lines.

32. The method of claim 31 comprising forming the doped isolation region within the lines of active area between immediately adjacent inner source/drain regions.

33. The method of claim 31 wherein the forming the doped isolation regions and the forming the inner source/drain regions comprise respective ion implantings, the ion implanting for the inner source/drain regions occurring before the ion implanting for the doped isolation region.

34. The method of claim 31 wherein the forming the doped isolation regions and the forming the outer source/drain regions comprise respective ion implantings, the ion implanting for the outer source/drain regions occurring after the ion implanting for the doped isolation region.

35. The method of claim 34 wherein the forming of the inner source/drain regions comprises an ion implanting, the ion implanting for the inner source/drain regions occurring before the ion implanting for the doped isolation region.

36. The method of claim 30 comprising forming the gate lines within individual of the pairs of gate lines to be parallel one another.

37. The method of claim 36 comprising forming the data/sense lines to be perpendicular relative to the gate line pairs.

38. The method of claim 30 comprising forming the data/sense lines and the gate lines to be longitudinally straight.

39. The method of claim 30 comprising forming the inner source/drain regions to individually be directly against a sidewall of individual of the buried data/sense lines.

40. The method of claim 30 comprising forming the gate lines within individual of the pairs of gate lines to be parallel and longitudinally straight relative one another.

41. The method of claim 40 comprising forming the data/sense lines to be perpendicular relative to the pairs of gate lines.

42. A method of forming a plurality of vertical transistor devices;

individual devices comprising an outer source/drain region, an inner source/drain region, and a channel region each formed within an active area;

a gate line operably proximate a sides of multiple channel regions;

a plurality of buried data/sense lines angling beneath the gate lines;

the inner source/drain regions individual electrically coupling to individual buried data/sense lines, the method comprising;

forming lines of active area alternating with lines of dielectric isolation within a semiconductor substrate;

etching buried data/sense line trenches into the lines of active area and lines of dielectric isolation, the buried data/sense line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation, individual lines of dielectric isolation underlying multiple buried data/sense line trenches;

forming the data/sense lines within the buried data/sense line trenches;

etching gate line trenches into the semiconductor substrate, the gate line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation and bifurcating the active area between two immediately adjacent data/sense lines;

forming the conductive gate lines within the gate line trenches; and

forming the outer and inner source/drain regions and the channel regions within the active area.

43. The method of claim 42 comprising forming the outer source/drain regions to individually have an outer target contact area having a trapezoidal shaped perimeter considered horizontally.

44. The method of claim 42 comprising forming the outer source/drain regions to individually have an outer target contact area having a pentagonal shaped perimeter considered horizontally.

45. The method of claim 42 comprising forming a charge storage component electrically coupled to individual of the outer source/drain regions.

46. The method of claim 45 wherein the charge storage component is directly against the individual outer source/drain region and directly against the dielectric isolation.

47. The method of claim 45 wherein,

the charge storage component is formed directly against the individual outer source/drain region;

the individual outer source/drain region is formed to have an outer target contact area having a trapezoidal shaped perimeter considered horizontally or a pentagonal shaped perimeter considered horizontally; and

the charge storage component is formed to be directly against only a portion of the individual outer target contact area.

48. The method of claim 47 comprising forming the inner source/drain regions to be directly against bottoms of the individual buried data/sense lines.

49. The method of claim 42 comprising forming a doped isolation region within the lines of active area between immediately adjacent buried data/sense lines.