VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT

• US 20150236031A1
• Filed: 02/18/2015
• Published: 08/20/2015
• Est. Priority Date: 02/18/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: NIEL, Stephan, REGNIER, Arnaud, LA ROSA, Francesco, DELALLEAU, Julien, MANTELLI, Marc
• Granted Patent: US 9,543,311 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Claims

1. A memory cell, comprising:

a semiconductor substrate having a trench;

a vertical selection gate extending in the trench in the substrate;

a floating gate extending above the substrate;

a horizontal control gate extending above the floating gate, the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, and the floating gate includes an electrically floating doped region, implanted at an intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

2. The memory cell according to claim 1 wherein the trench is covered with a dielectric layer comprising a thicker region near a surface of the substrate, and the floating gate comprises a protuberance which extends beneath the surface of the substrate in the thicker region of the dielectric layer and has a face opposite a portion of the vertical selection gate.

3. The memory cell according to claim 1, comprising an embedded layer that forms a collective source plane for collecting programming currents and configured to program the memory cell.

4. A device, comprising:

a semiconductor substrate having a trench;

a plurality of memory cells arranged in pairs of memory cells, each pair of memory cells includes a first and a second memory cell, each of the first and the second memory cell including;

a shared vertical selection gate extending in the trench in the substrate between the first memory cell and the second memory cell;

a horizontal control gate;

a floating gate extending above the substrate, the horizontal control gate extending above the floating gate, each floating gate extends above a portion of the shared vertical selection gate, over a non-zero overlap distance, and the floating gate includes an electrically floating doped region, implanted at an intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

5. The device of claim 4, further comprising a memory circuit in the substrate, the memory circuit including the plurality of memory cells, the plurality of memory cells being arranged in a memory array.

6. The device of claim 5 wherein the memory circuit includes a control circuit configured to program the plurality of memory cells, configured to apply electric potentials to the substrate, to the vertical selection gate, to the horizontal control gate and to drain and source regions of each memory cell, so that hot electrons are injected into the floating gate.

7. The device of claim 4 wherein the trench is covered with a dielectric layer includes a thicker region near a surface of the substrate, and the floating gate includes a protuberance that extends beneath the surface of the substrate in the thicker region of the dielectric layer and has a face opposite a portion of the vertical selection gate.

8. The device of claim 7 wherein the memory circuit includes a control circuit configured to erase each memory cell by tunnel effect that is configured to apply electric potentials to the vertical selection gate and the horizontal control gate of the memory cells, so that electric charges are extracted from the floating gate and collected by the vertical selection gate through the protuberance of the floating gate and the dielectric material extending between the protuberance and the vertical selection gate.

9. A method of manufacturing on a semiconductor substrate an electrically programmable memory cell, comprising:

etching a trench in the substrate, through a hard mask;

depositing on walls of the trench a first dielectric layer;

depositing on the substrate a first conductive layer and etching the first conductive layer to form a vertical selection gate extending in the trench;

depositing on the substrate a second dielectric layer;

depositing on the second dielectric layer a second conductive layer; and

forming a floating gate by etching the second conductive layer, the forming the floating gate including forming the floating gate to partially overlap the vertical selection gate over a non-zero overlap distance;

forming in the memory cell an electrically floating doped region situated at an intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate by tilt implanting dopants in a region of the substrate situated on a high edge of the trench and beneath the hard mask, the implanting performed through a vertical wall of the trench, the implanting occurring before depositing the first dielectric layer on the walls of the trench.

10. The method according to claim 9 wherein the second conductive layer is etched from a photolithography layout defining between a proximal edge of the floating gate and a corresponding proximal edge of the vertical selection gate a theoretical overlap distance at least equal to a photolithography tolerance.

11. The method according to claim 9, comprising a preliminary implanting in the substrate a conductive plane forming a source line for the memory cell.

12. The method according to claim 9, comprising producing in the dielectric layer covering the trench, a thicker region situated near a surface of the substrate.

13. The method according to claim 12, comprising making a hollow in the thicker region of the dielectric layer.

14. The method according to claim 13 wherein making the hollow including forming the hollow to extend beneath the surface of the substrate and so that the floating gate has a protuberance extending in the hollow and having a face opposite a portion of the vertical selection gate.

15. The method according to claim 9, comprising depositing a third dielectric layer on the second conductive layer and depositing a third conductive layer on the third dielectric layer, and simultaneously etching the third conductive layer and the second conductive layer, to form a horizontal control gate on the floating gate.