SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTORS HAVING A SURROUNDING GATE AND A WORK-FUNCTION METAL AROUND AN UPPER SIDEWALL

• US 20150236105A1
• Filed: 03/30/2015
• Published: 08/20/2015
• Est. Priority Date: 01/24/2013
• Status: Abandoned Application

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: MASUOKA, FUJIO, NAKAMURA, HIROKI
• Application Number:
  US14/672,448
• Publication Number:
  US 20150236105A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer. A fourth step includes depositing, planarizing, and etching-back a first interlayer insulating film to expose an upper portion of the pillar-shaped semiconductor layer, depositing a first metal, and etching the metal to form a first sidewall around the upper portion of the pillar-shaped semiconductor layer.

Claims

1. A semiconductor device, comprising:

a pillar-shaped semiconductor layer;

a gate insulating film formed around said pillar-shaped semiconductor layer;

a gate electrode formed around said gate insulating film;

a gate line connected to said gate electrode; and

a first sidewall composed of a first metal and formed around a sidewall of an upper portion of said pillar-shaped semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a first metal line formed on an upper portion of said pillar-shaped semiconductor layer and on said first sidewall.

3. The semiconductor device according to claim 1, wherein said semiconductor layers are silicon layers.

4. The semiconductor device according to claim 3, wherein said metal of said first sidewall has a work function between 4.0 eV and 4.2 eV.

5. The semiconductor device according to claim 3, wherein said metal of said first sidewall has a work function between 5.0 eV and 5.2 eV.

6. The semiconductor device according to claim 1, wherein said first sidewall has a laminated structure of said gate insulating film and said first metal.

7. A semiconductor device, comprising a first metal forming a sidewall around an upper portion of a semiconductor pillar.