AMORPHOUS SILICON PASSIVATED CONTACTS FOR BACK CONTACT BACK JUNCTION SOLAR CELLS
First Claim
1. A back contact back junction photovoltaic solar cell comprising:
- a semiconductor light absorbing layer having a front side and a backside;
base regions and emitter regions on said semiconductor light absorbing layer backside;
an amorphous silicon passivating layer on said base regions;
a first level base and emitter metallization, said first level metallization contacting said emitter regions and contacting said amorphous silicon passivating on said base regions;
an electrically insulating backplane on said first level metallization;
a second level metallization contacting said first level metallization through conductive vias in said electrically insulating dielectric.
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Accused Products
Abstract
Passivated contact structures and fabrication methods for back contact back junction solar cells are provided. According to one example embodiment, a back contact back junction photovoltaic solar cell is described that has a semiconductor light absorbing layer having a front side and a backside having base regions and emitter regions. An amorphous silicon passivating layer is positioned on the base regions. A first level base and emitter metallization contacts the emitter regions and the amorphous silicon passivating layer on the base regions. An electrically insulating backplane is positioned on the first level base and emitter metallization. A second level metallization contacts the first level base and emitter metallization through conductive vias in the electrically insulating backplane.
9 Citations
2 Claims
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1. A back contact back junction photovoltaic solar cell comprising:
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a semiconductor light absorbing layer having a front side and a backside; base regions and emitter regions on said semiconductor light absorbing layer backside; an amorphous silicon passivating layer on said base regions; a first level base and emitter metallization, said first level metallization contacting said emitter regions and contacting said amorphous silicon passivating on said base regions; an electrically insulating backplane on said first level metallization; a second level metallization contacting said first level metallization through conductive vias in said electrically insulating dielectric. - View Dependent Claims (2)
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Specification