LOW POWER LOW LATENCY PROTOCOL FOR DATA EXCHANGE

• US 20150237580A1
• Filed: 02/19/2015
• Published: 08/20/2015
• Est. Priority Date: 02/20/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: YU, Andy I-Fong, LIU, Honghao, TUDORANCEA, Andrei, SARDAR, Zeeshan Asad, MACHA, Lakshmi Narayana
• Granted Patent: US 10,200,951 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/0251 using monitoring of local events, e.g. events related to user activity
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Certain aspects of the present disclosure relate to techniques for processing (e.g., such as tasks for wireless communications and/or multimedia). According to certain aspects, a method for low power low latency data exchange generally includes providing timing information from a first processing entity to a second processing entity indicating when the second processing entity is to next process a message exchange between the first and second entities using a shared memory space, taking action to exit a low power state, based on the timing information, to access the shared memory space to process the message exchange, and entering the low power state after processing the message exchange.

Claims

1. A method for processing by a first processing entity of a device, comprising:

providing timing information to a second processing entity indicating when the second processing entity is to next process a message exchange between the first and second processing entities using a shared memory space;

taking action to exit a low power state, based on the timing information, to access the shared memory space to process the message exchange; and

entering the low power state after processing the message exchange.

2. The method of claim 1, wherein:

the device comprises a wireless device; and

the first and second processing entities are configured to process tasks related to wireless communications.

3. The method of claim 1, wherein the first and second processing entities are configured to process tasks related to multimedia processing.

4. The method of claim 3, wherein the message exchange is related to at least one of audio codecs, video frames, or graphics data.

5. The method of claim 1, wherein the first and second processing entities are configured to process tasks related to processing sensor data.

6. The method of claim 1, wherein the timing information is provided via the shared memory space.

7. The method of claim 1, wherein the shared memory space comprises at least one of a shared physical memory or a low latency interface (LLI).

8. The method of claim 1, wherein taking action to exit a low power state comprises programming a timer local to at least one of the first or second processing entities.

9. The method of claim 1, wherein the first processing entity comprises a modem subsystem and the second processing entity comprises a voice subsystem.

10. The method of claim 9, further comprising adjusting the timing information to switch between different rates of packet exchanges between the modem and voice subsystems.

11. The method of claim 10, wherein the different rates correspond to durations for packet exchange used for voice over long term evolution (VoLTE) or video telephony over long term evolution (VTLTE) communications.

12. The method of claim 9, wherein:

the timing information is designed to ensure the voice subsystem provides vocoder packet samples to the shared memory space prior to the modem exiting the low power state; and

taking action to exit the low power state comprises taking action to ensure the modem exits the low power state in time to process the vocoder packet samples.

13. The method of claim 9, wherein:

taking action to exit the low power state comprises taking action to ensure the modem exits the low power state in time to demodulate received signals; and

the timing information is designed to ensure the voice subsystem exits a low power state to process the demodulated received signals.

14. The method of claim 1, wherein the first and second processing entities reside on a same integrated circuit.

15. The method of claim 1, wherein the first and second processing entities are part of a common processor.

16. The method of claim 1, wherein the first and second processing entities are connected via a serial bus.

17. An apparatus, comprising:

a first processing entity configured to;

provide timing information to a second processing entity indicating when the second processing entity it to next process a message exchange between the first and second processing entities using a shared memory space;

take action to exit a low power state, based on the timing information, to access the shared memory space to process the message exchange; and

enter a low power state after processing the message exchange;

the second processing entity; and

a shared memory.

18. The apparatus of claim 17, wherein:

the apparatus comprises a wireless device; and

the first and second processing entities are configured to process tasks related to wireless communications.

19. The apparatus of claim 17, wherein the timing information is provided via the shared memory space.

20. The apparatus of claim 17, wherein the first processing system is configured to take action to exit a low power state by programming a timer local to at least one of the first or second processing entities.

21. The apparatus of claim 17, wherein the first processing entity comprises a modem subsystem and the second processing entity comprises a voice subsystem.

22. The apparatus of claim 21, wherein the first processing entity is further configured to adjust the timing information to switch between different rates of packet exchanges between the modem and voice subsystems.

23. The apparatus of claim 22, wherein the different rates correspond to durations for packet exchange used for voice over long term evolution (VoLTE) or video telephony over long term evolution (VTLTE) communications.

24. The apparatus of claim 21, wherein:

the timing information is designed to ensure the voice subsystem provides vocoder packet samples to the shared memory space prior to the modem exiting the low power state; and

the first processing system is configured to take action to exit the low power state by taking action to ensure the modem exits the low power state in time to process the vocoder packet samples.

25. The apparatus of claim 21, wherein:

the first processing system is configured to take action to exit the low power state by taking action to ensure the modem exits the low power state in time to demodulate received signals; and

the timing information is designed to ensure the voice subsystem exits a low power state to process the demodulated received signals.

26. The apparatus of claim 17, wherein the first and second processing entities reside on a same integrated circuit.

27. The apparatus of claim 17, wherein the first and second processing entities are part of a common processor.

28. The apparatus of claim 17, wherein the first and second processing entities are connected via a serial bus.

29. An apparatus for processing by a first processing entity of a device, comprising:

means for providing timing information to a second processing entity indicating when the second processing entity is to next process a message exchange between the first and second processing entities using a shared memory space;

means for taking action to exit a low power state, based on the timing information, to access the shared memory space to process the message exchange; and

means for entering the low power state after processing the message exchange.

30. A computer-readable medium storing computer executable code for processing by a first processing entity of a device, comprising:

code for providing timing information to a second processing entity indicating when the second processing entity is to next process a message exchange between the first and second processing entities using a shared memory space;

code for taking action to exit a low power state, based on the timing information, to access the shared memory space to process the message exchange; and

code for entering the low power state after processing the message exchange.