FLASH-DRAM HYBRID MEMORY MODULE

• US 20150242313A1
• Filed: 09/17/2014
• Published: 08/27/2015
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott H., Bhakta, Jayesh
• Granted Patent: US 9,158,684 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

Claims

1. (canceled)

2. A memory module comprising:

a first plurality of data signal lines forming a first data bus;

a second plurality of data signal lines forming a second data bus;

a third plurality of data signal lines forming a data bus;

a data manager coupled to the data bus, the first data bus, and the second data bus, wherein the memory module is couplable to a memory controller of a host system using the data bus, a control bus, and an address bus;

a non-volatile memory subsystem coupled to the data manager using the first data bus, the non-volatile memory subsystem operable to communicate data signals with the data manager by way of the first data bus;

a volatile memory subsystem coupled to the data manager using the second data bus, the volatile memory subsystem operable to communicate data signals with the data manager by way of the second data bus; and

a controller operable to receive one or more memory access commands from the memory controller of the host system by way of the control bus and the address bus, the controller operable to generate at least one of a first, second and third plurality of signals in response to the one or more memory access commands received from the memory controller of the host system, the controller operable to direct (i) operation of the non-volatile memory subsystem using the first plurality of signals, (ii) operation of the volatile memory subsystem using the second plurality of signals, and (iii) operation of the data manager using the third plurality of signals.

3. The memory module of claim 2, wherein, in response to the first plurality of signals, data signals are communicated between the non-volatile memory subsystem and the data manager by way of the first data bus.

4. The memory module of claim 2, wherein, in response to the second plurality of signals, data signals are communicated between the volatile memory subsystem and the data manager by way of the second data bus.

5. The memory module of claim 2, wherein, in response to the third plurality of signals, data signals are communicated between the data manager and at least one of (i) the memory controller of the host system by way of the data bus, (ii) the non-volatile memory subsystem by way of the first data bus, and (iii) the volatile memory subsystem by way of the second data bus.

6. The memory module of claim 2, wherein each of the data bus, the first data bus, and the second data bus includes bi-directional data signal lines.

7. The memory module of claim 2, wherein the data manager further comprises a data formatting subsystem operable, based on control information received from the controller, to format data to be transferred between any two or more of the memory controller of the host system, the volatile memory subsystem, and the non-volatile memory subsystem.

8. The memory module of claim 7, wherein the data manager further comprises a data formatting subsystem operable, in response to the third plurality of signals received from the controller, to format data to be transferred between any two or more of the memory controller of the host system, the volatile memory subsystem, and the non-volatile memory subsystem.

9. The memory module of claim 2, wherein the controller is operable to receive the one or more memory access commands from the memory controller of the host system using a protocol of the volatile memory subsystem.

10. The memory module of claim 6, wherein the protocol of the volatile memory subsystem is a JEDEC standard double data rate (DDR) protocol.

11. The memory module of claim 10, wherein the volatile memory subsystem includes at least one memory circuit, memory device, or memory die, and the controller communicates with the volatile memory subsystem using the protocol of the volatile memory subsystem.

12. The memory module of claim 10, wherein the controller communicates with the non-volatile memory subsystem using a protocol of the non-volatile memory subsystem.

13. The memory module of claim 12, wherein the protocol of the non-volatile memory subsystem is different from the protocol of the volatile memory subsystem.

14. The memory module of claim 2, wherein the memory module is in communication with the memory controller of the host system by way of a JEDEC standard double data rate (DDR) protocol.

15. The memory module of claim 2, wherein the controller is operable to configure a unified memory space of the memory module using at least a first portion of the volatile memory subsystem and a first portion of the non-volatile memory subsystem, the controller operable to present the unified memory space as a volatile memory space to the memory controller of the host system.

16. The memory module of claim 15, wherein the memory controller of the host system accesses the unified memory space using a standard protocol of the volatile memory subsystem.

17. The memory module of claim 16, wherein the standard protocol of the volatile memory subsystem is a JEDEC standard double data rate (DDR) protocol used for accessing standard DDR DRAM.

18. A memory module comprising:

a data manager couplable to a memory controller of a host system using a data bus, the data manager operable to communicate data signals with the memory controller of the host system by way of the data bus using a first protocol;

a non-volatile memory subsystem coupled to the data manager using a first data bus, the non-volatile memory subsystem operable to communicate data signals with the data manager by way of the first data bus using a second protocol;

a volatile memory subsystem coupled to the data manager using a second data bus, the volatile memory subsystem operable to communicate data signals with the data manager by way of the second data bus using the first protocol; and

a controller operable to receive one or more commands from the memory controller of the host system via a control bus and an address bus using the first protocol, and in response to the one or more commands from the memory controller of the host system, the controller is operable to direct (i) operation of the non-volatile memory subsystem using a first plurality of signals, (ii) operation of the volatile memory subsystem using a second plurality of signals, and (iii) operation of the data manager using a third plurality of signals,

wherein in response to any one or more of the first, second, and third plurality of signals the data manager communicates data signals with at least one of the memory controller of the host system, the volatile memory subsystem, and the non-volatile memory subsystem.

19. The memory module of claim 18, wherein the first, second and third plurality of signals are generated by the controller in response to the one or more commands from the memory controller of the host system.

20. The memory module of claim 18, wherein the first protocol is a JEDEC standard double data rate (DDR) protocol, and wherein the second protocol is different from the first protocol.

21. The memory module of claim 18, wherein, based on instructions received from the controller using the third plurality of signals, the data manager is operable to control data traffic between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem.

22. The memory module of claim 18, wherein, in response to the third plurality of signals received from the controller, the data manager is operable to control data traffic between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem.

23. The memory module of claim 21, wherein the data traffic control relates to any one or more of data flow rate, data transfer size, data buffer size, data transfer bit width, formatting information, direction of data flow, and a starting time of a data transfer.

24. The memory module of claim 18, wherein the data manager is configured as a bi-directional data transfer fabric having two or more sets of data ports coupled to any one or more of the memory controller of the host system, the volatile memory subsystem, and the non-volatile memory subsystem.

25. The memory module of claim 24, wherein at least one set of data ports is operated by the data manager to independently or concurrently transfer data to or from one or more memory segments of the volatile or non-volatile memory subsystems.