SEMICONDUCTOR DEVICE

• US 20150243753A1
• Filed: 05/01/2015
• Published: 08/27/2015
• Est. Priority Date: 11/25/2010
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: SUEKAWA, Eisuke, ORITSUKI, Yasunori, TARUI, Yoichiro
• Granted Patent: US 9,842,906 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n⁺-source region formed in an upper portion of an n⁻-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Claims

1. (canceled)

2. A semiconductor device, comprising:

a main transistor cell with a gate insulating film formed on a silicon carbide semiconductor layer, a gate electrode formed on said gate insulating film, and a source region that is an impurity region formed in an upper portion of said semiconductor layer;

an interlayer insulating film covering said gate electrode;

a source electrode connected to said source region while extending on said interlayer insulating film;

a gate pad connected to said gate electrode;

a barrier metal layer interposed between said source electrode and said interlayer insulating film, and between said gate pad and said gate electrode, said barrier metal layer formed both on said source region and under said gate pad, said barrier metal layer contacting a surface of said interlayer insulating film;

a temperature sensing diode formed on said semiconductor layer and including a p-type polysilicon and an n-type polysilicon;

an anode electrode connected to said p-type polysilicon; and

a cathode electrode connected to said n-type polysilicon,

wherein said barrier metal layer is also interposed between said p-type polysilicon and said anode electrode as well as between said n-type polysilicon and said cathode electrode.

3. The semiconductor device according to claim 2, wherein said barrier metal layer is any one of a TiSi layer, TiN layer, a two-layer structure including a TiSi layer and a Ti layer, and a two-layer structure including a TiN layer and a Ti layer.

12. The semiconductor device according to claim 2, wherein:

said barrier metal layer extends continuously from the top portion of said interlayer insulating film to a side portion of said interlayer insulating film.

15. The semiconductor device according to claim 2, wherein:

said barrier metal layer has been patterned together with said source electrode and said gate pad.

18. The semiconductor device according to claim 2, further comprising:

a silicide layer in ohmic contact with said source region, said silicide layer disposed between said source region and said source electrode;

wherein

said barrier metal layer is further disposed between said silicide layer and said source electrode.

4. A semiconductor device, comprising:

a main transistor cell with a gate insulating film formed on a silicon carbide semiconductor layer, a gate electrode formed on said gate insulating film, and a source region that is an impurity region formed in an upper portion of said semiconductor layer;

an interlayer insulating film covering said gate electrode;

a source electrode connected to said source region while extending on said interlayer insulating film;

a gate pad connected to said gate electrode; and

a barrier metal layer interposed between said source electrode and said interlayer insulating film, and between said gate pad and said gate electrode, said barrier metal layer formed both on said source region and under said gate pad, said barrier metal layer contacting a surface of said interlayer insulating film,

wherein said barrier metal layer includes Ti.

5. The semiconductor device according to claim 4, wherein said barrier metal layer is a Ti layer having a thickness of 40 nm or more.

6. The semiconductor device according to claim 4, wherein said barrier metal layer is a TiSi layer having a thickness of 130 nm or more.

7. The semiconductor device according to claim 4, wherein said barrier metal layer has a two-layer structure including a TiSi layer and a Ti layer.

8. The semiconductor device according to claim 4, wherein said barrier metal layer has a two-layer structure including a TiN layer and a Ti layer.

13. The semiconductor device according to claim 4, wherein:

said barrier metal layer extends continuously from the top portion of said inter layer insulating film to a side portion of said interlayer insulating film.

16. The semiconductor device according to claim 4, wherein:

said barrier metal layer has been patterned together with said source electrode and said gate pad.

19. The semiconductor device according to claim 4, further comprising:

a silicide layer in ohmic contact with said source region, said silicide layer disposed between said source region and said source electrode;

wherein

said barrier metal layer is further disposed between said silicide layer and said source electrode.

21. The semiconductor device according to claim 4, wherein:

a thickness of the barrier metal layer is defined to reduce a reduction in a threshold voltage less than 2 V during an HTGB test conducted for 240 hours by applying a negative voltage to the gate of the MOSFET, the HTGB test conducted with a gate-to-source voltage set at −

20 V and with an ambient temperature set at 125°

C.

9. A semiconductor device, comprising:

a main transistor cell with a gate insulating film formed on a silicon carbide semiconductor layer, a gate electrode formed on said gate insulating film, and a source region that is an impurity region formed in an upper portion of said semiconductor layer;

an interlayer insulating film covering said gate electrode;

a source electrode connected to said source region while extending on said interlayer insulating film;

a gate pad connected to said gate electrode; and

a barrier metal layer interposed between said source electrode and said interlayer insulating film, and between said gate pad and said gate electrode, said barrier metal layer formed both on said source region and under said gate pad, said barrier metal layer contacting a surface of said interlayer insulating film

wherein;

a thickness of the barrier metal layer is greater than or equal to 40 nm.

10. The semiconductor device according to claim 9, wherein:

a thickness of the barrier metal layer is greater than or equal to 50 nm.

11. The semiconductor device according to claim 10, wherein:

a thickness of the barrier metal layer is greater than or equal to 130 nm.

14. The semiconductor device according to claim 9, wherein:

said barrier metal layer extends continuously from the top portion of said interlayer insulating film to a side portion of said inter layer insulating film.

17. The semiconductor device according to claim 9, wherein:

said barrier metal layer has been patterned together with said source electrode and said gate pad.

20. The semiconductor device according to claim 9, further comprising:

a silicide layer in ohmic contact with said source region, said silicide layer disposed between said source region and said source electrode;

wherein

said barrier metal layer is further disposed between said silicide layer and said source electrode.