INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME

• US 20150243756A1
• Filed: 04/28/2015
• Published: 08/27/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Obradovic, Borna J., Bowen, Robert C., Rodder, Mark S.
• Granted Patent: US 9,583,590 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include In_yGa_1−yAs, and y is in a range of about 0.3 to about 0.5.

Claims

1. A method of forming a finFET, the method comprising:

forming a fin-shaped channel region comprising indium (In) on a substrate;

forming a deep source/drain region adjacent to the channel region on the substrate; and

forming a source/drain extension region between the channel region and the deep source/drain region, wherein;

opposing sidewalls of the source/drain extension region contact the channel region and the deep source/drain region, respectively; and

the source/drain extension region comprises In_yGa<sub>1−

y</sub>As, and y is in a range of about 0.3 to about 0.5.

2. The method of claim 1, wherein an indium concentration in the channel region is greater than an indium concentration in the source/drain extension region.

3. The method of claim 2, wherein forming the channel region comprises forming the channel region comprising In_xGa₁₋

xAs, and x is in a range of about 0.5 to about 0.6.

4. The method of claim 3, wherein x is about 0.53.

5. The method of claim 4, wherein y is about 0.4.

6. The method of claim 3, wherein an indium concentration in the deep source/drain region is greater than the indium concentration in the channel region.

7. The method of claim 6, wherein forming the deep source/drain region comprises forming the deep source/drain region comprising In_zGa₁₋

zAs, z is in a range of about 0.6 to about 1.

8. The method of claim 6, further comprising forming a contact region contacting an upper surface of the deep source/drain region, wherein a portion of the deep source/drain region contacts the contact region and comprises pure InAs.

9. The method of claim 3, wherein the substrate comprises an InP substrate or In_aGa₁₋

aAs, and a is about 0.53 or less.

10. The method of claim 3, wherein:

the substrate comprises an InP substrate; and

forming the channel region comprising In_xGa<sub>1−

x</sub>As comprises forming an In_xGa<sub>1−

x</sub>As pattern that is lattice matched to the InP substrate.

11. The method of claim 1, wherein forming the channel region and the source/drain extension region comprises:

forming a preliminary channel region on the substrate;

forming a mask pattern on the preliminary channel region;

etching the preliminary channel region using the mask pattern as an etching mask to form the channel region; and

epitaxially growing the source/drain extension region using the channel region as a seed layer.

14. The method of claim 1, wherein forming the deep source/drain region comprises epitaxially growing the deep source/drain region using the source/drain extension region as a seed layer.

15. The method of claim 1, wherein:

forming the deep source/drain region comprises forming a first deep source/drain region that is adjacent to a first sidewall of the channel region such that the opposing sidewalls of the source/drain extension region contact the first sidewall of the channel region and a sidewall of the first deep source/drain region, respectively; and

the method further comprises forming a second deep second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

17. The method of claim 1, wherein a width of the source/drain extension region in a direction from the channel region to the deep source/drain region is about 10 nm.

18. The method of claim 1, further comprising forming a gate electrode overlying the channel region, wherein one of the opposing sidewalls of the source/drain extension region that contacts a sidewall of the channel region is substantially aligned to a sidewall of the gate electrode such that a junction is formed in the source/drain extension region.

12-13. -13. (canceled)

16. (canceled)

19. A method of forming a finFET, the method comprising:

forming a fin-shaped channel region comprising a first semiconductor material on a substrate;

forming a source/drain region on a sidewall of the channel region on the substrate; and

forming a barrier layer between the sidewall of the channel region and a sidewall of the source/drain region, wherein;

the barrier layer comprises the first semiconductor material and a second semiconductor material; and

a first semiconductor material concentration in the barrier layer is less than a first semiconductor material concentration in the channel region.

20. The method of claim 19, wherein a first semiconductor material concentration in the source/drain region and the first semiconductor material concentration in the barrier layer are different.

21. The method of claim 20, wherein:

the first semiconductor material comprises Indium (In), and the second semiconductor material comprises gallium (Ga); and

the first semiconductor material concentration in the source/drain region is greater than the first semiconductor material concentration in the channel region.

22. The method of claim 21, wherein forming the channel region comprises forming the channel region comprising In_xGa₁₋

xAs, and x is in a range of about 0.5 to about 0.6.

32. The method of claim 19, wherein forming the channel region and the barrier layer comprises:

forming a preliminary channel region on the substrate;

forming a mask pattern on the preliminary channel region;

etching the preliminary channel region using the mask pattern as an etching mask to form the channel region; and

epitaxially growing the barrier layer using the channel region as a seed layer.

34. The method of claim 19, wherein:

forming the source/drain region comprises forming a first source/drain region on a first sidewall of the channel region such that the barrier layer is disposed between the first sidewall of the channel region and a sidewall of the first source/drain region; and

the method further comprises forming a second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

35. The method of claim 19, wherein a width of the barrier layer in a direction from the channel region to the source/drain region is about 10 nm.

23-31. -31. (canceled)

33. (canceled)

36-49. -49. (canceled)