CIRCUIT INTERFACING SINGLE-ENDED INPUT TO AN ANALOG TO DIGITAL CONVERTER

• US 20150244385A1
• Filed: 11/20/2014
• Published: 08/27/2015
• Est. Priority Date: 02/27/2014
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Alladi, Dinesh Jagannath, Dagher, Elias Hani, Hafiz, Omar
• Application Number:
  US14/549,445
• Publication Number:
  US 20150244385A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 1/0629 Anti-aliasing
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/186 in feedforward mode, i.e. by determining the range to be selected directly from the input signal
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing

Abstract

In embodiments, a circuit includes a single-ended input coupled to a first input of a differential filter. The differential filter is coupled to an analog to digital converter (ADC), and the single-ended input includes an input DC bias voltage level and an input signal. A reference generator circuit is coupled to a second input of the differential filter. The reference generator circuit generates a reference bias voltage. The differential filter includes a first filter coupled to the singled ended input and to the ADC and a second filter coupled to the reference generator circuit and to the ADC. The first filter is configured to receive the input DC bias voltage level and input signal. The second filter is configured to receive the reference bias voltage.

Claims

1. A circuit comprising:

a single-ended input coupled to a first input of a differential filter, wherein the differential filter is coupled to an analog to digital converter (ADC), and wherein the single-ended input comprises an input DC bias voltage level and an input signal; and

a reference generator circuit coupled to a second input of the differential filter, the reference generator circuit generating a reference bias voltage,

wherein the differential filter comprises;

a first filter coupled to the singled ended input and to the ADC, the first filter configured to receive the input DC bias voltage level and input signal; and

a second filter coupled to the reference generator circuit and to the ADC, the second filter configured to receive the reference bias voltage.

2. The circuit of claim 1, wherein the reference generator circuit comprises a low noise reference generator configured to generate the reference bias voltage.

3. The circuit of claim 2, wherein the reference generator circuit comprises a reference buffer configured to buffer the reference bias voltage.

4. The circuit of claim 3, wherein the reference generator circuit comprises a third filter configured to couple ground noise to an input of the reference buffer, and wherein the coupled ground noise tracks ground noise coupled to the single-ended input.

5. The circuit of claim 3, wherein the output of the reference buffer is coupled to the second input of the differential filter to provide the reference bias voltage to the second filter.

6. The circuit of claim 2, wherein the reference generator circuit comprises a third filter configured to filter noise from the reference bias voltage.

7. The circuit of claim 1, wherein:

the first filter comprises one or more first resistor capacitor filters, and

the second filter comprises one or more second resistor capacitor filters.

8. The circuit of claim 7, wherein the one or more first resistor capacitor filters and the one or more second resistor capacitor filters filter noise at high frequencies.

9. The circuit of claim 7, wherein the one or more second resistor capacitor filters comprise a resistor in series with a reference buffer of the reference generator circuit, wherein a resistance of the resistor is larger than an output resistance of the reference buffer.

10. The circuit of claim 1, further comprising:

a differential capacitor network coupled differentially to the first filter and the second filter.

11. The circuit of claim 10, wherein:

the first filter comprises a first resistor coupled to the differential capacitor network, and

the second filter comprises a second resistor coupled to the differential capacitor network.

12. The circuit of claim 1, wherein the differential filter comprises a differential anti-aliasing filter.

13. The circuit of claim 1, wherein the differential filter is coupled to a sample and hold switched capacitor network of the ADC.

14. A system comprising:

a single-ended input coupled to a first input of a differential filter, wherein the differential filter is coupled to an analog to digital converter (ADC), and wherein the single-ended input comprises an input DC bias voltage level and an input signal;

a reference generator circuit configured to generate a reference bias voltage; and

a reference buffer coupled to the reference generator circuit to receive the reference bias voltage, and coupled to a second input of the differential filter to provide the reference bias voltage to the second input,

wherein the differential filter comprises;

a first filter coupled to the singled ended input and to the ADC, the first filter configured to receive the input DC bias voltage level and input signal; and

a second filter coupled to the reference buffer and to the ADC, the second filter configured to receive the reference bias voltage.

15. The system of claim 14, wherein the reference generator circuit comprises a third filter configured to couple ground noise to an input of the reference buffer, and wherein the coupled ground noise tracks ground noise coupled to the single-ended input.

16. The system of claim 14, wherein the reference generator circuit comprises a third filter configured to filter noise from the reference bias voltage.

17. The system of claim 14, wherein:

the first filter comprises one or more first resistor capacitor filters, and

the second filter comprises one or more second resistor capacitor filters.

18. The system of claim 14, further comprising:

a differential capacitor network coupled differentially to the first filter and the second filter.

19. The system of claim 18, wherein:

the first filter comprises a first resistor coupled to the differential capacitor network, and

the second filter comprises a second resistor coupled to the differential capacitor network.

20. The system of claim 14, wherein the differential filter is coupled to a sample and hold switched capacitor network of the ADC.