Memory Systems and Block Copy Methods Thereof
First Claim
1. A method of operating a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store N-bit data, each of the plurality of second memory cells being configured to store 1-bit data, N being an integer greater than two, the method comprising:
- reading a first page of data from a first portion of the plurality of first memory cells;
performing an error checking and correction (ECC) operation on the first page of the data to thereby generate a first page of ECC-processed data;
programming the first page of ECC-processed data in the plurality of second memory cells;
reading the first page of ECC-processed data that is programmed in the plurality of second memory cells;
programming, in a second portion of the plurality of first memory cells, the first page of ECC-processed data that is read from the plurality of second memory cells;
after the programming the first page of ECC-processed data in the second portion of the plurality of first memory cells, re-reading the first page of ECC-processed data that is programmed in the plurality of second memory cells; and
re-programming, in the second portion of the plurality of first memory cells, the first page of ECC-processed data that is re-read from the plurality of second memory cells.
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Abstract
Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.
23 Citations
30 Claims
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1. A method of operating a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store N-bit data, each of the plurality of second memory cells being configured to store 1-bit data, N being an integer greater than two, the method comprising:
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reading a first page of data from a first portion of the plurality of first memory cells; performing an error checking and correction (ECC) operation on the first page of the data to thereby generate a first page of ECC-processed data; programming the first page of ECC-processed data in the plurality of second memory cells; reading the first page of ECC-processed data that is programmed in the plurality of second memory cells; programming, in a second portion of the plurality of first memory cells, the first page of ECC-processed data that is read from the plurality of second memory cells; after the programming the first page of ECC-processed data in the second portion of the plurality of first memory cells, re-reading the first page of ECC-processed data that is programmed in the plurality of second memory cells; and re-programming, in the second portion of the plurality of first memory cells, the first page of ECC-processed data that is re-read from the plurality of second memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data, the method comprising:
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reading a first page of data from a first portion of the plurality of first memory cells; performing an error checking and correction (ECC) operation on the first page of the data to thereby generate a first page of ECC-processed data; programming the first page of ECC-processed data in the plurality of second memory cells; reading the first page of ECC-processed data, a second page of data and a third page of data that are programmed in the plurality of second memory cells; programming, in a second portion of the plurality of first memory cells, the first page of ECC-processed data, the second page of data and the third page of data that are read from the plurality of second memory cells; after the programming the first page of ECC-processed data, the second page of data and the third page of data in the second portion of the plurality of first memory cells, re-reading the first page of ECC-processed data, the second page of data and the third page of data that are programmed in the plurality of second memory cells; and re-programming, in the second portion of the plurality of first memory cells, the first page of ECC-processed data, the second page of data and the third page of data that are re-read from the plurality of second memory cells. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory system comprising:
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a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store N-bit data, each of the plurality of second memory cells being configured to store 1-bit data, N being an integer greater than two; and a controller configured to perform an error checking and correction (ECC) operation on a first page of data that is read from a first portion of the plurality of first memory cells, configured to generate a first page of ECC-processed data, and configured to output the first page of ECC-processed data to the nonvolatile memory device, wherein the nonvolatile memory device is configured to program the first page of ECC-processed data in the plurality of second memory cells, the nonvolatile memory device is configured to read the first page of ECC-processed data that is programmed in the plurality of second memory cells, the nonvolatile memory device is configured to program, in a second portion of the plurality of first memory cells, the first page of ECC-processed data that is read from the plurality of second memory cells, and the nonvolatile memory device is configured to re-program, in the second portion of the plurality of first memory cells, the first page of ECC-processed data that is read from the plurality of second memory cells. - View Dependent Claims (24, 25, 26)
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27. A memory system comprising:
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a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data; and a controller configured to perform an error checking and correction (ECC) operation on a first page of data that is read from a first portion of the plurality of first memory cells, configured to generate a first page of ECC-processed data, and configured to output the first page of ECC-processed data to the nonvolatile memory device, wherein the nonvolatile memory device is configured to program the first page of ECC-processed data in the plurality of second memory cells, the nonvolatile memory device is configured to read the first page of ECC-processed data, a second page of data and a third page of data that are programmed in the plurality of second memory cells, the nonvolatile memory device is configured to program, in a second portion of the plurality of first memory cells, the first page of ECC-processed data, the second page of data and the third page of data that are read from the plurality of second memory cells, and the nonvolatile memory device is configured to re-program, in the second portion of the plurality of first memory cells, the first page of ECC-processed data, the second page of data and the third page of data that are read from the plurality of second memory cells. - View Dependent Claims (28, 29, 30)
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Specification