COMPONENT PLACEMENT WITH REPACKING FOR PROGRAMMABLE LOGIC DEVICES

• US 20150248512A1
• Filed: 02/28/2014
• Published: 09/03/2015
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Shen, Yinan, Zhao, Jun
• Granted Patent: US 10,262,096 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.

Claims

1. A computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD);

determining a layout comprising positions of components of the PLD configured to perform the operations;

performing a timing analysis on the layout; and

selectively adjusting the positions of the components using the timing analysis.

2. The method of claim 1, wherein the adjusting comprises:

identifying a signal path between at least a subset of the components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location.

3. The method of claim 2, wherein the target location corresponds to a particular component position within a particular logic block of the PLD.

4. The method of claim 1, wherein the determining comprises assigning the components to logic blocks of the PLD.

5. The method of claim 4, wherein the adjusting comprises moving each adjusted component from its first assigned logic block to a second different logic block.

6. The method of claim 4, wherein the components are lookup tables implemented in the logic blocks.

7. The method of claim 1, wherein the determining comprises performing a simulated annealing placement process to determine the positions of the components.

8. The method of claim 7, wherein the timing analysis and the adjusting are performed during the simulated annealing placement process.

9. The method of claim 7, wherein the timing analysis and the adjusting are performed after the simulated annealing placement process.

10. The method of claim 1, further comprising routing connections between the components after the simulated annealing placement process, wherein the timing analysis and the adjusting are performed after the routing.

11. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising;

receiving a design identifying operations to be performed by a programmable logic device (PLD),

determining a layout comprising positions of components of the PLD configured to perform the operations,

performing a timing analysis on the layout, and

selectively adjusting the positions of the components using the timing analysis.

12. The system of claim 11, wherein the adjusting comprises:

identifying a signal path between at least a subset of the components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location.

13. The system of claim 12, wherein the target location corresponds to a particular component position within a particular logic block of the PLD.

14. The system of claim 11, wherein the determining comprises assigning the components to logic blocks of the PLD.

15. The system of claim 14, wherein the adjusting comprises moving each adjusted component from its first assigned logic block to a second different logic block.

16. The system of claim 11, wherein the determining comprises performing a simulated annealing placement process to determine the positions of the components.

17. The system of claim 16, wherein the timing analysis and the adjusting are performed during the simulated annealing placement process.

18. The system of claim 16, wherein the timing analysis and the adjusting are performed after the simulated annealing placement process.

19. The system of claim 11, wherein the method further comprises routing connections between the components after the simulated annealing placement process, wherein the timing analysis and the adjusting are performed after the routing.

20. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:

identifying a signal path between at least a subset of the components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location.