METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS

• US 20150249036A1
• Filed: 03/03/2014
• Published: 09/03/2015
• Est. Priority Date: 03/03/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Cai, Xiuyu, Xie, Ruilong, Cheng, Kangguo, Khakifirooz, Ali
• Granted Patent: US 9,536,877 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Claims

1. A method of forming source/drain conductive contacts to first and second source/drain regions, said first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, said second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than said first gate pitch dimension, wherein said first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure, the method comprising:

forming a first layer of insulating material above said first and second source/drain regions;

forming a second layer of insulating material above said first layer of insulating material;

forming first and second contact openings above said first and second source/drain regions, wherein forming said first contact opening removes substantially all of said first layer of insulating material positioned above said first source/drain region and between facing sidewall spacers on said first pair of transistor devices having said first gate pitch, and wherein forming said second contact opening removes some, but not all, of said first layer of insulating material positioned above said second source/drain region and between facing sidewall spacers on said second pair of transistor devices having said second gate pitch, said second contact opening extending through a portion of said first layer of insulating material;

performing an etching process through said first contact opening to remove the facing sidewall spacers on said first pair of transistor devices and thereby expose facing edges of the gate structures on said first pair of transistor devices;

performing a common deposition and etch process sequence to form first and second low-k sidewall spacers within said first and second contact openings, respectively, wherein said first low-k sidewall spacer contacts the exposed facing edges of the gate structure of said first pair of transistor devices and said second low-k sidewall spacer is formed on said first layer of insulating material within said second contact opening; and

forming source/drain conductive contacts in said first and second contact openings.

2. The method of claim 1, wherein said gate structures are replacement gate structures that are comprised of a high-k gate insulation layer and at least one layer of metal that acts as a portion of a gate electrode.

3. The method of claim 2, wherein said first and second contact openings extend through said second layer of insulating material.

4. The method of claim 3, wherein said first low-k sidewall spacer engages a portion of said second layer of insulating material within said first contact opening and wherein said second low-k sidewall spacer engages a portion of said second layer of insulating material within said second contact opening.

5. The method of claim 1, wherein said source/drain conductive contacts are comprised of tungsten.

6. The method of claim 1, wherein said first gate pitch is 60 nm or less.

7. The method of claim 1, wherein said second layer of insulating material is formed on said first layer of insulating material.

8. The method of claim 1, wherein said source/drain regions are raised source/drain regions comprised of an epitaxially deposited layer of semiconductor material.

9-14. -14. (canceled)

15. A method of forming source/drain conductive contacts to first and second source/drain regions, said first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, said second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than said first gate pitch dimension, wherein said first and second pairs of transistor devices have a replacement gate structure and sidewall spacers positioned adjacent said replacement gate structure, the method comprising:

forming a first layer of insulating material above said first and second source/drain regions;

forming a second layer of insulating material above said first layer of insulating material;

forming first and second contact openings above said first and second source/drain regions, wherein forming said first contact opening removes substantially all of said first layer of insulating material positioned above said first source/drain region and between facing sidewall spacers on said first pair of transistor devices having said first gate pitch, and wherein forming said second contact opening removes some, but not all, of said first layer of insulating material positioned above said second source/drain region and between facing sidewall spacers on said second pair of transistor devices having said second gate pitch, said second contact opening extending through a portion of said first layer of insulating material;

performing an etching process through said first contact opening to remove said facing sidewall spacers on said first pair of transistor devices and thereby expose a high-k gate insulation layer on each of the facing edges of said replacement gate structures on said first pair of transistor devices;

performing a common deposition and etch process sequence to form first and second low-k sidewall spacers within said first and second contact openings, respectively, wherein said first low-k sidewall spacer contacts said high-k gate insulation layer on each of said exposed facing edges of said replacement gate structure of said first pair of transistor devices and said second low-k sidewall spacer is formed on said first layer of insulating material within said second contact opening; and

forming source/drain conductive contacts in said first and second contact openings.

16. The method of claim 15, wherein said first and second contact openings extend through said second layer of insulating material.

17. The method of claim 16, wherein said first low-k sidewall spacer engages a portion of said second layer of insulating material within said first contact opening and wherein said second low-k sidewall spacer engages a portion of said second layer of insulating material within said second contact opening.

18. The method of claim 17, wherein said first gate pitch is 60 nm or less.

19. The method of claim 15, wherein said second layer of insulating material is formed on said first layer of insulating material.

20. The method of claim 15, wherein said source/drain regions are raised source/drain regions comprised of an epitaxially deposited layer of semiconductor material.