THREE DIMENSION INTEGRATED CIRCUITS EMPLOYING THIN FILM TRANSISTORS

• US 20150249096A1
• Filed: 12/23/2014
• Published: 09/03/2015
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Tacho Holdings, LLC
• Original Assignee: Tacho Holdings, LLC
• Inventors: Agan, Tommy Allen, Lupino, James John
• Granted Patent: US 9,853,053 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/165 Auxiliary circuits
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

Claims

1. An integrated circuit device, comprising

a memory array arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance,

whereby each conductive line of the first conductive lines or the second conductive lines or both first and second conductive lines, is electrically coupled to at least one thin film transistor and

whereby said transistors are substantially positioned above or below the memory array

2. The device according to claim 1 whereby the memory array is a RRAM, MRAM or PCRAM array

3. The device according to claim 1 whereby the memory array is embedded memory of a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, or other integrated circuit

4. The device according to claim 1 whereby a bidirectional selector switch is located between each memory cell and one of the said conductive lines

5. An integrated circuit device according to claim 1, further comprising

at least two memory arrays separated from each other in the vertical direction, each memory array arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance,

whereby each conductive line of the first conductive lines or the second conductive lines or both first and second conductive lines, is electrically coupled to at least one thin film transistor and

whereby said transistors are substantially positioned above or below a memory array

6. The device according to claim 5 whereby a memory array is a resistance random access memory array

7. The device according to claim 5 whereby a memory array is embedded memory of a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, or other integrated circuit

8. The device according to claim 1, whereby a buffer memory is employed to enable I/O from an external source at a higher clock speed than the I/O to a nonvolatile memory array

9. The device according to claim 5, whereby a buffer memory is employed to enable I/O from an external source at a higher clock speed than the I/O to a nonvolatile memory array

11. The device according to claim 5, comprising of a plurality of layers of memory arrays and logic blocks comprised of thin film transistors and interconnects between the layers in the vertical direction whereby, a memory array is arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance,

wherein each conductive line of the first conductive lines or the second conductive lines or both first and second conductive lines, is connected to at least one thin film transistor and

wherein said transistors are substantially positioned above or below a memory array

12. The device according to claim 11 whereby the device comprises either a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, MEMS or a hybrid thereof

13. The device according to claim 11 whereby the device comprises an energy storage device, microdisplay, RF device or image sensor

10. An integrated circuit device comprising of a plurality of logic blocks comprised of thin film transistors and interconnects between logic blocks in the vertical direction

14. An integrated circuit device comprising I/O circuitry comprised of thin film transistors

15. The device according to claim 14 whereby the core circuitry of the device is based on CMOS transistors and substantially all of the I/O circuitry resides above the core circuitry

16. A device according to claim 14 comprising of a first substrate, I/O circuitry comprised of thin film transistors residing on said first substrate, whereby core circuitry related to a portion of said I/O circuitry resides on a second substrate and is connected to said I/O circuitry

17. The device according to claim 16 whereby the first substrate is a printed circuit board

18. The device according to claim 16 further comprising of I/O bus lines residing on or within said first substrate, whereby the I/O bus lines connect first I/O circuitry of a first core circuitry to second I/O circuitry of a second core circuitry

19. The device according to claim 18 whereby a first core circuity is a microprocessor, FPGA, ASIC or ASSP residing on the second substrate

20. The device according to claim 18 whereby a second core circuitry is related to memory