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THREE DIMENSION INTEGRATED CIRCUITS EMPLOYING THIN FILM TRANSISTORS

  • US 20150249096A1
  • Filed: 12/23/2014
  • Published: 09/03/2015
  • Est. Priority Date: 09/10/2012
  • Status: Active Grant
First Claim
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1. An integrated circuit device, comprisinga memory array arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance,whereby each conductive line of the first conductive lines or the second conductive lines or both first and second conductive lines, is electrically coupled to at least one thin film transistor andwhereby said transistors are substantially positioned above or below the memory array

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