METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

• US 20150249153A1
• Filed: 02/28/2014
• Published: 09/03/2015
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Morin, Pierre, Loubet, Nicolas
• Granted Patent: US 9,660,080 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Claims

1. A method for straining a channel region of an FET, the method comprising:

forming trenches in a first semiconductor substrate having a first semiconductor material to define a first region of the FET that contains a channel region of the FET; and

converting, after formation of the trenches, a first portion of the first region to a different chemical composition such that the converted first portion imparts strain to the channel region.

2. The method of claim 1, wherein the FET is a FD-SOI FET.

3. The method of claim 1, wherein the FET is a finFET.

4. The method of claim 3, wherein the first region comprises a fin of a finFET and has a width between about 1 nm and about 25 nm.

5. The method of claim 3, wherein forming trenches comprises etching trenches in the first semiconductor substrate to define at least one fin for at least one finFET.

6. The method of claim 1, further comprising:

covering a second portion of the first region;

depositing a converting material in the trenches; and

heating the substrate to a temperature at which at least some component of the converting material enters the portion of the first region.

7. The method of claim 6, wherein the converting material comprises a second semiconductor material that is of a different chemical composition than the first semiconductor material.

8. The method of claim 6, wherein the converting material is SiGe or SiC and the first semiconductor material is Si.

9. The method of claim 6, wherein the heating comprises oxidizing the converting material.

10. The method of claim 6, wherein the depositing comprises epitaxially growing the converting material.

11. The method of claim 6, wherein the depositing comprises depositing an amorphous composition of the converting material.

12. The method of claim 6, further comprising depositing a filling material to fill the trenches before heating the substrate.

13. The method of claim 12, wherein the filling material is an oxide.

14. The method of claim 12, further comprising transforming a portion of the converting material to an oxide.

15. The method of claim 12, further comprising:

removing a portion of the filling material to expose the channel region; and

forming a gate structure at the channel region.

16. A strained-channel finFET comprising:

a fin having a channel region formed of a first semiconductor material having a first chemical composition;

a strain-inducing portion formed in the fin that induces strain in the channel region of the fin, wherein the strain-inducing portion comprises the first semiconductor material that has been converted to a second semiconductor material having a second chemical composition that is different from the first chemical composition.

17. The strained-channel finFET of claim 16, wherein the second semiconductor material includes a chemical additive compared to the first semiconductor material, and wherein a concentration of the chemical additive varies across the fin.

18. The strained-channel finFET of claim 17, wherein the concentration of the chemical additive is higher at edge regions of the fin than at a center of the fin.

19. The strained-channel finFET of claim 17, wherein the chemical additive is germanium or carbon and the first semiconductor is silicon.

20. The strained-channel finFET of claim 16, wherein the fin has a width between about 1 nm and about 25 nm.

21. The strained-channel finFET of claim 16, further comprising a layer of covering material that covers the channel region of the fin but does not cover the strain-inducing portion of the fin.

22. The strained-channel finFET of claim 21, wherein the covering material comprises an oxide or a nitride.

23. The strained-channel finFET of claim 16, further comprising a gate structure formed at the channel region of the fin.

24. The strained-channel finFET of claim 16, further comprising a continuous layer of insulating material between the fin and a bulk region of a substrate on which the fin is formed.

25. The strained-channel finFET of claim 16, wherein the strain-inducing portion has a defect density greater than 10⁵ defects/cm².

26. A finFET structure on a substrate comprising:

a fin formed in a first semiconductor material of a first chemical composition, wherein the fin has a length extending parallel to a surface of the substrate and a height extending perpendicular to a surface of the substrate;

a covering layer that covers a first portion of the fin and does not cover a second portion of the fin, wherein a boundary between the first portion and second portion extends along a length of the fin; and

a converting material in direct contact with the second portion of the fin, wherein the converting material contains a chemical component that, when introduced into the second portion of the fin, creates compressive or tensile stress along a length of the fin.

27. The finFET of claim 26, wherein the fin has a width between about 1 nm and about 25 nm.

28. The finFET of claim 26, wherein the first semiconductor material is silicon.

29. The finFET of claim 28, wherein the chemical component is germanium or carbon.

30. The finFET of claim 28, wherein the converting material comprises epitaxial SiGe or SiC.

31. The finFET of claim 28, wherein the converting material comprises amorphous SiGe or SiC.

32. The finFET of claim 26, wherein the covering layer comprises an oxide or a nitride.