METHOD AND APPARATUS OF STRESSED FIN NMOS FINFET

• US 20150249155A1
• Filed: 05/19/2014
• Published: 09/03/2015
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: XU, Jeffrey Junhao, YEAP, Choh Fei
• Granted Patent: US 9,306,066 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Claims

1. A stressed fin FinFET device comprising:

a substrate;

a fin on the substrate, comprising a semiconductor material and extending along a longitudinal axis, the a longitudinal axis parallel to the substrate, extending, in a vertical direction, to a fin top at a fin height above the substrate; and

an embedded fin stressor element, wherein the fin stressor element is embedded in the fin, and wherein the fin stressor element is configured to urge an upward compression force within the fin, parallel to the vertical direction.

2. The stressed fin FinFET device of claim 1, wherein the semiconductor material includes silicon, and wherein the fin stressor element comprises silicon dioxide.

3. The stressed fin FinFET device of claim 2,

wherein the fin comprises a fin base and a fin active region,

wherein the active region includes a source region, a drain region, and a channel region,

wherein the channel region is between the source region and the drain region, wherein the fin base is proximal to the substrate, and

wherein the embedded fin stressor element is embedded in the fin base under the channel region.

4. The stressed fin FinFET device of claim 3, wherein the channel region is doped with a p+ dopant, and the source region and the drain region are doped with an n+ dopant.

5. The stressed fin FinFET device of claim 4,

wherein the fin includes a first vertical wall and a second vertical wall,

wherein the second vertical wall is parallel to the first vertical wall and spaced from the first vertical wall by a fin thickness,

wherein the embedded fin stressor element has a stressor element thickness in the vertical direction, a stressor element width in a direction of the fin thickness, and a stressor element length in a direction parallel to the longitudinal axis, and

wherein the stressor element width is equal to the fin thickness.

6. The stressed fin FinFET device of claim 5,

wherein the embedded fin stressor element and the fin are configured to meet at an upper major interface that is interior to the fin and is spaced a depth under the fin top in a depth direction that is opposite the vertical direction, and

wherein the embedded fin stressor element and the fin have a lower major interface that is spaced by the stressor element thickness under the upper major interface in the depth direction.

7. The stressed fin FinFET device of claim 6, wherein the embedded fin stressor element exerts, at the upper major interface, the upward compression force, wherein the upward compression force is against the channel region of the fin, wherein the upward compression force is in the vertical direction.

8. The stressed fin FinFET device of claim 7,

wherein the embedded fin stressor element is an embedded fin first stressor element,

wherein the stressed fin FinFET device further comprises an embedded fin second stressor element, and

wherein the embedded fin second stressor element is embedded in the fin base under the source region or under the drain region.

9. The stressed fin FinFET device of claim 8,

wherein the depth is a first depth,

wherein the stressor element thickness is a first stressor element thickness,

wherein the upper major interface is a first upper major interface and the lower major interface is a first lower major interface,

wherein the embedded fin second stressor element and the fin have a second upper major interface and a second lower major interface,

wherein the second upper major interface is interior to the fin and is spaced a second depth under the fin top in the depth direction, and

wherein the second lower major interface is spaced by a second stressor element thickness under the second upper major interface in the depth direction.

10. The stressed fin FinFET device of claim 9,

wherein the upward compression force is a first upward compression force,

wherein the fin second stressor element exerts, at the second upper major interface, a second upward compression force against the source region of the fin, and

wherein the second upward compression force is in the vertical direction.

11. The stressed fin FinFET device of claim 10, wherein one of the first depth and the second depth is greater than the other of the first depth and the second depth.

12. The stressed fin FinFET device of claim 10, wherein one of the first stressor element thickness and the second stressor element thickness is greater than the other of the first stressor element thickness and the second stressor element thickness.

13. The stressed fin FinFET device of claim 10,

wherein a sum of the first upward compression force and the second upward compression force is a total resultant upward compression force,

wherein the total resultant upward compression has a force distribution with respect to positions along the longitudinal axis.

14. The stressed fin FinFET device of claim 6,

wherein the embedded fin stressor element is an embedded fin first stressor element,

wherein the stressed fin FinFET device further comprises an embedded fin second stressor element and an embedded fin third stressor element,

wherein the embedded fin second stressor element is embedded in the fin base under the source region, and

wherein the embedded fin third stressor element is embedded in the fin base under the drain region

15. The stressed fin FinFET device of claim 14,

wherein the depth is a first depth,

wherein the upper major interface is a first upper major interface and the lower major interface is a first lower major interface,

wherein the embedded fin second stressor element and the fin have a second upper major interface,

wherein the second upper major interface is interior to the fin and is spaced a second depth under the fin top in the depth direction,

wherein the embedded fin third stressor element and the fin have a third upper major interface, and

wherein the third upper major interface is interior to the fin and is spaced a third depth under the fin top in the depth direction.

16. The stressed fin FinFET device of claim 15,

wherein the upward compression force is a first upward compression force,

wherein the embedded fin second stressor element exerts, at the second upper major interface, a second upward compression force against the source region of the fin,

wherein the second upward compression force is in the vertical direction,

wherein the embedded fin third stressor element exerts, at the third upper major interface, a third upward compression force against the drain region of the fin, and

wherein the third upward compression force is in the vertical direction.

17. The stressed fin FinFET device of claim 1, wherein the stressed fin FinFET is integrated in at least one semiconductor die.

18. The stressed fin FinFET device of claim 1, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the stressed fin FinFET device is integrated.

19. A stressed fin FinFET device comprising:

a substrate;

a fin, comprising a semiconductor material, having a fin width and extending in a vertical direction to a fin top at a fin height above the substrate, the fin having a fin base extending on the substrate along a longitudinal axis, and a fin active portion on the fin base and extending in the vertical direction to the fin top, the fin base having a height less than the fin height, the fin active portion having a source region, a drain region, and a channel region between the source region and the drain region;

a gate surrounding at least a portion of the channel region; and

an embedded fin stressor element, wherein the embedded fin stressor element is embedded under the fin active portion, and wherein the embedded fin stressor element is configured to urge a given compression force in the fin active portion, parallel to the vertical direction.

20. The FinFET device of claim 19,

wherein the semiconductor material includes silicon, and

wherein at least one embedded fin stressor element comprises silicon dioxide, and wherein at least one stressor element embedded in the fin base under the channel region.

21. The FinFET device of claim 20,

wherein the at least one embedded fin stressor element includes a first embedded silicon dioxide stressor element,

wherein the FinFET device includes a second embedded silicon dioxide stressor element, wherein the second embedded silicon dioxide stressor element is embedded in the fin base under one of the source region and the drain region, and

wherein the at least one embedded stressor element further includes a third embedded silicon dioxide stressor element, wherein the third embedded silicon dioxide stressor element is embedded in the fin base under the other of the source region and the drain region.

22. The stressed fin FinFET device of claim 21, wherein the channel region is doped with a p+ dopant, and the source region and the drain region are doped with an n+ dopant.

23. The stressed fin FinFET device of claim 19, wherein the embedded fin stressor element is a first embedded fin stressor element, and wherein the stressed fin FinFET device further includes a second embedded fin stressor element and a third embedded fin stressor element

wherein the second embedded fin stressor element is embedded in the fin base under one of the source region and the drain region, and

wherein the third embedded fin stressor element is embedded in the fin base under the other of the source region and the drain region.

24. The stressed fin FinFET device of claim 19, wherein the stressed fin FinFET is integrated in at least one semiconductor die.

25. The stressed fin FinFET device of claim 19, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the stressed fin FinFET device is integrated.

26. A method for providing vertical compression in a fin of a FinFET, comprising:

forming a semiconductor fin, of a silicon semiconductor material, and having a given channel region, on a substrate;

forming an oxygenation mask on the semiconductor fin, providing at least an exposed region under the given channel region;

performing oxidation on at least the exposed region under the given channel region, penetrating to form an oxidation region under the given channel region; and

forming a silicon dioxide layer, wherein the silicon dioxide layer is embedded under the given channel region of the semiconductor fin, by performing a Separation by Implantation of Oxygen (SIMOX) operation on at least the oxidation region under the given channel region.

27. The method of claim 26,

wherein the SIMOX operation includes a re-crystallization of the given channel region and at least the oxidation region under the given channel region,

wherein the SIMOX operation includes is configured to form the silicon dioxide layer during the re-crystallization, and

wherein the forming of the silicon dioxide layer includes a volume expansion that establishes a vertical compressive stress in the channel region.

28. The method of claim 27, wherein the forming the semiconductor fin is configured to form the semiconductor fin to further include a source region and a drain region,

wherein the exposed region under the channel region is a first exposed region, and wherein the forming the oxygenation mask on the semiconductor fin is configured to further provide a second exposed region, wherein the second exposed region is under the source region or under the drain region,

wherein the oxidation region is a first oxidation region, and wherein performing oxidation is configured to further perform oxidation on the second exposed region, penetrating to form a second oxidation region under the source region or under the drain region,

wherein the silicon dioxide layer is a first silicon dioxide layer, wherein the SIMOX operation is performed to include the second oxidation region to form a second silicon dioxide layer under the source region or under the drain region.

29. The method of claim 27, further comprising doping the channel region with a p+ dopant.

30. A computer-readable medium comprising computer-executable instructions that when executed by a computer connected to a semiconductor fabrication system cause computer to control the semiconductor fabrication system to:

form a semiconductor fin, of a silicon semiconductor material, having a given channel region, on a substrate;

form an oxygenation mask on the semiconductor fin, wherein the oxygenation mask provides at least an exposed region under the given channel region;

perform oxidation on at least the exposed region under the given channel region, penetrating to form an oxidation region under the given channel region; and

form a silicon dioxide layer, wherein the silicon dioxide layer is embedded under the given channel region of the semiconductor fin, by performing a Separation by Implantation of Oxygen (SIMOX) operation on at least the oxidation region under the given channel region,

wherein the SIMOX operation includes a re-crystallization of the given channel region and at least the oxidation region under the given channel region,

wherein SIMOX operation is configured to form the silicon dioxide layer during the re-crystallization, and

wherein the forming of the silicon dioxide layer includes a volume expansion that establishes a vertical compressive stress in the channel region.