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PACKET SCHEDULING IN A NETWORK PROCESSOR

  • US 20150249604A1
  • Filed: 02/28/2014
  • Published: 09/03/2015
  • Est. Priority Date: 02/28/2014
  • Status: Active Grant
First Claim
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1. A circuit for managing transmittal of packets, the circuit comprising:

  • a packet descriptor manager (PDM) configured to generate a metapacket from a command signal, the metapacket indicating a size and a destination of a packet to be transmitted by the circuit;

    a packet scheduling engine (PSE) configured to model transmission of the packet through a model of a network topology from the destination to the circuit, the PSE determining an order in which to transmit the packet among a plurality of packets based on the model transmission; and

    a packet engines and buffering (PEB) module configured to process the packet and cause the processed packet to be transmitted toward the destination according to the order determined by the PSE.

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