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SECURITY PROCESSING ENGINES, CIRCUITS AND SYSTEMS AND ADAPTIVE PROCESSES AND OTHER PROCESSES

  • US 20150249654A1
  • Filed: 05/14/2015
  • Published: 09/03/2015
  • Est. Priority Date: 07/08/2010
  • Status: Active Grant
First Claim
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1. A packet-processing electronic subsystem comprising:

  • a first data interface having an input for accepting first streaming data and having an output;

    a second data interface having an input for accepting second streaming data and having an output;

    a third data interface having an output for egress of third streaming data and having an input;

    a fourth data interface having an output for egress of fourth streaming data and having an input, the first, second, third, and fourth data interfaces being separate from one another;

    scheduler circuitry having inputs coupled to the outputs of the first and second interfaces, having outputs coupled to the inputs of the third, and fourth data interfaces, and including a packet memory, the scheduler circuitry having a security context cache interface, a packet header processor interface, an authentication interface, and an air cipher interface;

    a security context cache coupled to the security context cache interface of the scheduler circuitry and including a cache controller and cache storage for a security context;

    a packet header processor coupled to the packet header processor interface of the scheduler circuitry;

    an authentication module coupled to the authentication interface of the scheduler circuitry; and

    an air cipher module coupled to the air cipher interface of the scheduler circuitry, the air cipher module including processor and control circuitry.

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