PROGRAMMABLE INTERFACE-BASED VALIDATION AND DEBUG

• US 20150253387A1
• Filed: 05/26/2015
• Published: 09/10/2015
• Est. Priority Date: 09/26/2013
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gahoi, Anshul, Santhanagopal, Raghavendra, Babu, Pradeep Kumar
• Application Number:
  US14/721,216
• Publication Number:
  US 20150253387A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 13/28 Circuits for simultaneous or sequential presentation of more than one variable
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs

Abstract

A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.

Claims

1-20. -20. (canceled)

21. A method for validating a debugging a design under test comprising the steps of:

communicating to the design under test via a test connector including a shared test bus coupled to a first set of selected pins of the design under test;

receiving a downloadable test bench including a first set of test vectors from a first test control bus;

receiving a second set of test vectors from a second test control bus; and

selectively coupling one of the first set of test vectors and the second set of test vectors to the shared test bus.

22. The method of claim 21, wherein:

supplying the second set of test vectors from a debugger operable by a human to control execution of the first set of test vectors.

23. The method of claim 22, further comprising the step of:

transferring mastership of the shared test bus between the debugger and the downloadable test bench.

24. The method of claim 23, further comprising the step of:

transferring mastership of the shared test bus dependent upon a received command.

25. The method of claim 23, further comprising the step of:

transferring mastership of the shared test bus dependent upon contents of the first test control bus.

26. The method of claim 23, further comprising the step of:

transferring mastership of the shared test bus dependent upon contents of the second test control bus.

27. The method of claim 23, further comprising the step of:

transferring mastership of the shared test bus dependent upon an output of the design under test.

28. The method of claim 22, further comprising the step of:

validating performance of the design under test via the first set of test vectors coupled to the test connector.

29. The method of claim 21, further comprising the step of:

storing the first set of test vectors in an addressable memory.

30. The method of claim 29, further comprising the step of:

generating an address by which test vectors from the first set of test vectors are retrieved from the addressable memory via a program counter.

31. The method of claim 30, further comprising the step of:

changing the value of the program counter in response to a value of retrieved test vectors from the first set of test vectors.

32. The method of claim 31, further comprising the steps of:

retrieving a first portion of the first set of retrieved test vectors of the first set of test vectors;

applying the first set of selected pins of the test connector;

retrieving a second portion of the first set of retrieved test vectors of the first set of test vectors;

applying the second portion of the first set of retrieved test vectors a third test bus to a second set of selected pins of the test connector, wherein the second set of selected pins of the test connector includes selected pins that are different from the selected pins in the first set of selected pins.