Error Checking and Correction for NAND Flash Devices

• US 20150254129A1
• Filed: 03/05/2014
• Published: 09/10/2015
• Est. Priority Date: 03/05/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Authement, Shawn P., Kuang, Jente B., Nam, Gi-Joon
• Granted Patent: US 9,417,945 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

Claims

1. A method, in a Not AND (NAND) flash memory device, for providing hybrid error correction management, the method comprising:

providing a Not AND (NAND) flash memory module and a node controller coupled to the NAND flash memory module in the NAND flash memory device;

providing a hardware logic implemented error correction code (ECC) engine associated with the node controller;

configuring the node controller to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller; and

configuring the node controller to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

2. The method of claim 1, wherein the NAND flash memory device is one of a flash memory card coupled to a host system via a card slot of the host system or a portable NAND flash memory device.

3. The method of claim 1, wherein the first threshold number of error bits is set to a value causing a majority of error correction operations for data read from the NAND flash memory module to be performed by the hardware logic implemented ECC engine.

4. The method of claim 1, wherein the software logic implemented ECC engine:

assigns a read queue order number to read packets in a stream of read packets read from the NAND flash memory module;

tracks and arbitrates read queue order based on the assigned read queue order numbers; and

corrects errors in the read packets of the stream of read packets based on the read queue order.

5. The method of claim 1, wherein the first threshold number of error bits is a fixed value set during design of the NAND flash memory device based on iterative simulation of the executions of workloads on a model of the NAND flash memory device to generate a lower bound value for the first threshold number of error bits based on a determined aggregate access time of the workloads, and an upper bound value for the first threshold number of error bits based on a per access read latency of the workloads, and wherein the first threshold number of error bits is selected to be a value in a range defined by the lower bound value and the upper bound value.

6. The method of claim 1, wherein the first threshold number of error bits is a dynamically determined value during runtime operation of the NAND flash memory device, and wherein the first threshold number of error bits is set to a value via hardware implemented setting logic in the node controller.

7. The method of claim 6, wherein the first threshold number of error bits is set to the value via the hardware implemented setting logic in the node controller based on at least one of a determined type of workload being executed by a host system to which the NAND flash memory device is coupled, a number of errors encountered, or a detected latency in error correction operations.

8. The method of claim 1, wherein the software logic implemented ECC engine performs error correction operations for error bits up to and including a second threshold number of error bits, and wherein the second threshold number of error bits is dynamically set according to a determined type of workload for which data is read from the NAND flash memory module of the NAND flash memory device.

9. The method of claim 1, wherein the software logic implemented ECC engine comprises logic executing on one of a processor of a host computing device coupled to the NAND flash memory device or a processor integrated in the NAND flash memory device.

10. The method of claim 1, wherein the hardware logic implemented ECC engine is provided in a read engine of the node controller of the NAND flash memory device and outputs either corrected packets or uncorrected packets to a multiplexer of a node controller interface of the NAND flash memory device based on whether or not the error count is equal to or less than the first threshold number of error bits.

11. The method of claim 10, wherein the multiplexer outputs either corrected or uncorrected packets to interface logic of the NAND flash memory device based on whether or not the error count is equal to or less than the first threshold number of error bits, and wherein the interface logic comprises setting logic for setting a value of the first threshold number of error bits by providing a control signal back to the hardware logic implemented ECC engine to cause the hardware logic implemented ECC engine to be reconfigured to the value set by the setting logic.

12. A Not AND (NAND) flash memory device, comprising:

a Not AND (NAND) flash memory module;

a node controller coupled to the NAND flash memory module; and

a hardware logic implemented error correction code (ECC) engine associated with the node controller, wherein the node controller is configured to;

determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, perform correction of the error bits by the hardware logic implemented ECC engine associated with the node controller; and

forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

13. The NAND flash memory device of claim 12, wherein the NAND flash memory device is one of a flash memory card coupled to a host system via a card slot of the host system or a portable NAND flash memory device.

14. The NAND flash memory device of claim 12, wherein the first threshold number of error bits is set to a value causing a majority of error correction operations for data read from the NAND flash memory module to be performed by the hardware logic implemented ECC engine.

15. The NAND flash memory device of claim 12, wherein the software logic implemented ECC engine:

assigns a read queue order number to read packets in a stream of read packets read from the NAND flash memory module;

tracks and arbitrates read queue order based on the assigned read queue order numbers; and

corrects errors in the read packets of the stream of read packets based on the read queue order.

16. The NAND flash memory device of claim 12, wherein the first threshold number of error bits is a fixed value set during design of the NAND flash memory device based on iterative simulation of the executions of workloads on a model of the NAND flash memory device to generate a lower bound value for the first threshold number of error bits based on a determined aggregate access time of the workloads, and an upper bound value for the first threshold number of error bits based on a per access read latency of the workloads, and wherein the first threshold number of error bits is selected to be a value in a range defined by the lower bound value and the upper bound value.

17. The NAND flash memory device of claim 12, wherein the first threshold number of error bits is a dynamically determined value during runtime operation of the NAND flash memory device, and wherein the first threshold number of error bits is set to a value via hardware implemented setting logic in the node controller.

18. The NAND flash memory device of claim 17, wherein the first threshold number of error bits is set to the value via the hardware implemented setting logic in the node controller based on at least one of a determined type of workload being executed by a host system to which the NAND flash memory device is coupled, a number of errors encountered, or a detected latency in error correction operations.

19. The NAND flash memory device of claim 12, wherein the software logic implemented ECC engine performs error correction operations for error bits up to and including a second threshold number of error bits, and wherein the second threshold number of error bits is dynamically set according to a determined type of workload for which data is read from the NAND flash memory module of the NAND flash memory device.

20. The NAND flash memory device of claim 12, wherein the software logic implemented ECC engine comprises logic executing on one of a processor of a host computing device coupled to the NAND flash memory device or a processor integrated in the NAND flash memory device.