MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD

• US 20150254131A1
• Filed: 07/29/2014
• Published: 09/10/2015
• Est. Priority Date: 03/07/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TORII, Osamu, HARADA, Kohsuke
• Application Number:
  US14/445,198
• Publication Number:
  US 20150254131A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

According to one embodiment, there is provided a memory controller that controls nonvolatile memory of K bits/cell, first and second bits of the K bits corresponding to first and second pages, the memory controller including an encoder configured to encode unit data to write in a first page to generate a parity; and a decoder configured to perform an error correction process using the readout unit data and the parity; where readout of the first page is carried out using 2^K−1 first voltage values, readout of the second page is carried out using a second voltage value, which is less in number than 2^K−1, and a bit value of the second page is selected based on a bit value of the first page of after the error correction.

Claims

1. A memory controller configured to control nonvolatile memory including a memory cell in which data of K bits is storable in one memory cell, where K is an integer greater than or equal to two, a first bit of the data of K bits representing data of a first page and a second bit representing data of a second page, the memory controller comprising:

an encoder configured to encode unit data to write in the first page to generate a parity;

a memory control unit configured to perform control to write the unit data and the parity in the nonvolatile memory at time of write in the first page, and to perform control to write the unit data in the nonvolatile memory at time of write in the second page;

a decoder configured to perform an error correction process using the unit data and the parity read out from the nonvolatile memory; and

a readout control unit configured to instruct the memory control unit to carry out readout using 2^K−

1 first voltage values at time of readout from the first page and instruct the memory control unit to carry out readout using a second voltage values, which are different from the first voltage value and less in number than 2^K−

1, at time of readout from the second page, and to select a bit value of the second page from a determination results of the bit value by the second voltage values based on the bit value of after the error correction of the first page;

wherein the memory control unit performs the readout from the nonvolatile memory based on an instruction from the readout control unit.

2. The memory controller according to claim 1, wherein

K=2;

and

the second voltage value is an intermediate value of the largest first voltage value and the second largest first voltage value, and an intermediate value of the second largest first voltage value and the third largest first voltage value.

3. The memory controller according to claim 1, wherein

K=2;

the encoder encodes the unit data to write in the second page to generate a parity;

the memory control unit performs the control to write the unit data and the parity in the nonvolatile memory at the time of the write in the second page; and

the decoder carries out the error correction process based on the unit data and the parity of the second page determined based on the bit value of the first page.

4. The memory controller according to claim 1, wherein

K=3;

and

the second voltage value includes an intermediate value of one of the first voltage values and the first voltage value next largest to the one first voltage value.

5. The memory controller according to claim 1, wherein

K=3;

a third bit of the data of K bits represents data of a third page; and

the readout control unit instructs the memory control unit to carry out the readout using a third voltage value, which is different from the first voltage value and less in number than 2^K−

1, at time of readout from the third page, and selects a bit value of the third page from a determination result of the bit value by the third voltage value based on the bit value of the second page determined based on the bit value of the first page.

6. The memory controller according to claim 5, wherein

the encoder encodes the unit data to write in the second page to generate a parity;

the memory control unit performs the control to write the unit data and the parity in the nonvolatile memory at the time of write in the second page;

the decoder carries out an error correction process based on the unit data and the parity of the second page determined based on the bit value of the first page; and

a fixed bit value of the second page is the bit value of the second page of after the error correction process.

7. The memory controller according to claim 1, wherein

K=3;

a third bit of the data of K bits represents data of a third page; and

the readout control unit instructs the memory control unit to carry out the readout using a third voltage value, which is different from the first voltage value and less in number than 2^K−

1, at the time of readout from the third page, and selects a bit value of the third page from a determination result of the bit value by the third voltage value based on the bit value of after the error correction of the first page.

8. The memory controller according to claim 1, wherein an assignment of the bit value with respect to 2^K charge amount distributions of the memory cell is an assignment in which a bit value to be assigned to the charge amount distribution is incremented by one bit in an order of large charge amount or small charge amount.

9. A storage device comprising:

nonvolatile memory including a memory cell in which data of K bits is storable in one memory cell, where K is an integer greater than or equal to two, a first bit of the data of K bits representing data of a first page and a second bit representing data of a second page; and

a memory controller configured to control the nonvolatile memory, wherein

the memory controller includes,

an encoder configured to encode unit data to write in the first page to generate a parity,

a memory control unit configured to perform control to write the unit data and the parity in the nonvolatile memory at time of write in the first page, and to perform control to write the unit data in the nonvolatile memory at time of write in the second page;

a decoder configured to perform an error correction process using the unit data and the parity read out from the nonvolatile memory, and

a readout control unit configured to instruct the memory control unit to carry out readout using 2^K−

1 first voltage values at time of readout from the first page and instruct the memory control unit to carry out readout using a second voltage values, which are different from the first voltage value and less in number than 2^K−

1, at time of readout from the second page, and to select a bit value of the second page from a determination results of the bit value by the second voltage values based on the bit value of after the error correction of the first page; and

the memory control unit performs the readout from the nonvolatile memory based on an instruction from the readout control unit.

10. The storage device according to claim 9, wherein

K=2;

and

the second voltage value is an intermediate value of the largest first voltage value and the second largest first voltage value, and an intermediate value of the second largest first voltage value and the third largest first voltage value.

11. The storage device according to claim 9, wherein

K=2;

the encoder encodes the unit data to write in the second page to generate a parity;

the memory control unit performs the control to write the unit data and the parity in the nonvolatile memory at the time of the write in the second page; and

the decoder carries out the error correction process based on the unit data and the parity of the second page determined based on the bit value of the first page.

12. The storage device according to claim 9, wherein

K=3;

and

the second voltage value includes an intermediate value of one of the first voltage values and the first voltage value next largest to the one first voltage value.

13. The storage device according to claim 9, wherein

K=3;

a third bit of the data of K bits represents data of a third page; and

the readout control unit instructs the memory control unit to carry out the readout using a third voltage value, which is different from the first voltage value and less in number than 2^K−

1, at time of readout from the third page, and selects a bit value of the third page from a determination result of the bit value by the third voltage value based on the bit value of the second page determined based on the bit value of the first page.

14. The storage device according to claim 13, wherein

the encoder encodes the unit data to write in the second page to generate a parity;

the memory control unit performs the control to write the unit data and the parity in the nonvolatile memory at the time of write in the second page;

the decoder carries out an error correction process based on the unit data and the parity of the second page determined based on the bit value of the first page; and

a fixed bit value of the second page is the bit value of the second page of after the error correction process.

15. The storage device according to claim 9, wherein

K=3;

a third bit of the data of K bits represents data of a third page; and

the readout control unit instructs the memory control unit to carry out the readout using a third voltage value, which is different from the first voltage value and less in number than 2^K−

1, at the time of readout from the third page, and selects a bit value of the third page from a determination result of the bit value by the third voltage value based on the bit value of after the error correction of the first page.

16. The storage device according to claim 9, wherein an assignment of the bit value with respect to 2^K charge amount distributions of the memory cell is an assignment in which a bit value to be assigned to the charge amount distribution is incremented by one bit in an order of large charge amount or small charge amount.

17. A memory control method for controlling nonvolatile memory including a memory cell in which data of K bits is storable in one memory cell, where K is an integer greater than or equal to two, a first bit of the data of K bits representing data of a first page and a second bit representing data of a second page, the memory control method comprising:

encoding unit data to write in the first page, and generating a parity;

controlling to write the unit data and the parity in the nonvolatile memory at time of write in the first page, and controlling to write the unit data in the nonvolatile memory at time of write in the second page;

performing an error correction process using the unit data and the parity read out from the nonvolatile memory;

carrying out readout using 2^K−

1 first voltage values at time of readout from the first page; and

carrying out readout using a second voltage values, which are different from the first voltage values and less in number than 2^K−

1, at time of readout from the second page, and selecting a bit value of the second page from a determination results of the bit value by the second voltage values based on the bit value of after the error correction of the first page.