Virtual Critical Path (VCP) System and Associated Methods

• US 20150254384A1
• Filed: 03/05/2014
• Published: 09/10/2015
• Est. Priority Date: 03/05/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dumchin, Yan, Minz, Leonid, Baram, Yair, Tomashev, Michael, Kaplan, Yevgeny, Zilberman, Suzanna
• Granted Patent: US 9,825,638 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.

Claims

1. A semiconductor chip, comprising:

a critical path circuit defined to operate in accordance with a system clock signal, the critical path circuit having a critical path signal timing characteristic; and

a virtual critical path circuit defined to operate in accordance with a special clock signal, the virtual critical path circuit defined separate from the critical path circuit, the special clock signal generated separate from the system clock signal, the virtual critical path circuit defined to have a virtual critical path signal timing characteristic substantially equal to the critical path signal timing characteristic, the virtual critical path circuit including computational circuitry defined to compute an output value based on an input value, the virtual critical path circuit including comparison circuitry defined to compare the output value computed by the computational circuitry with an expected result value associated with the input value, wherein a match between the output value computed by the computational circuitry and the expected result value indicates that a frequency of the special clock signal is acceptable, and wherein a difference between the output value computed by the computational circuitry and the expected result value indicates that the frequency of the special clock signal is not acceptable.

2. The semiconductor chip as recited in claim 1, wherein the virtual critical path circuit includes special clock signal control circuitry defined to increase the frequency of the special clock signal between different operations of the computational circuitry to compute the output value based on the input value so as to determine a maximum acceptable frequency of the special clock signal, wherein the maximum acceptable frequency of the special clock signal is a largest frequency of the special clock signal that provides for correct computation of the output value by the computational circuitry based on comparison of the output value with the expected result value.

3. The semiconductor chip as recited in claim 2, wherein the virtual critical path circuit is defined to direct the computational circuitry to compute a first output value based on a first input value and to compute a second output value based on a second input value in an alternating manner in accordance with successive cycles of the special clock signal.

4. The semiconductor chip as recited in claim 3, wherein the virtual critical path circuit includes circuitry for communicating a determined value of the maximum acceptable frequency of the special clock signal to system clock signal control circuitry to enable the adjustment of a frequency of the system clock signal to match the maximum acceptable frequency of the special clock signal.

5. The semiconductor chip as recited in claim 4, wherein the virtual critical path circuit includes synchronization circuitry defined to synchronize transfer of signals between a domain of the system clock signal and a domain of the special clock signal.

6. The semiconductor chip as recited in claim 1, wherein the computational circuitry is defined separate from the critical path circuit, and wherein the computational circuitry operates independent of the critical path circuit.

7. The semiconductor chip as recited in claim 6, wherein the computational circuitry is located near the critical path circuit on the semiconductor chip such that the computational circuitry and the critical path circuit are subject to similar process variation during manufacture, and such that the computational circuitry and the critical path circuit are subject to similar voltage and temperature during operation of the semiconductor chip.

8. A virtual critical path circuit, comprising:

an input register for storing a programmable input value;

computational circuitry defined to perform mathematical operations on the input value, the computational circuitry defined to operate in accordance with a special clock signal, the special clock signal generated separate from a system clock signal, the computational circuitry defined to have a signal timing characteristic substantially equivalent to a signal timing characteristic of a critical path circuit defined to operate in accordance with the system clock signal;

an output register for storing an output value generated by the computational circuitry; and

comparison circuitry defined to compare the output value to an expected result value to determine if the output value is correct, wherein a correct output value indicates that a frequency of the special clock signal is acceptable, and wherein an incorrect output value indicates that the frequency of the special clock signal is not acceptable.

9. The virtual critical path circuit as recited in claim 8, wherein the computational circuitry is defined separate from the critical path circuit, and wherein the computational circuitry operates independent of the critical path circuit.

10. The virtual critical path circuit as recited in claim 9, wherein the computational circuitry is located near the critical path circuit on a semiconductor chip such that the computational circuitry and the critical path circuit are subject to similar process variation during manufacture, and such that the computational circuitry and the critical path circuit are subject to similar voltage and temperature during operation of the semiconductor chip.

11. The virtual critical path circuit as recited in claim 8, wherein the input register is a first input register for storing a programmable value of a first input value, and wherein the virtual critical path circuit includes a second input register for storing a programmable value of a second input value, the virtual critical path circuit including a multiplexer connected to receive as inputs the first and second input values from the first and second input registers, the multiplexer defined to alternate submission of the first and second input values on successive cycles of the special clock signal as input to the computational circuitry, and wherein the comparison circuitry is defined to compare the output value to a first expected result value when the first input value is operated on by the computational circuitry, and wherein the comparison circuitry is defined to compare the output value to a second expected result value when the second input value is operated on by the computational circuitry.

12. The virtual critical path circuit as recited in claim 11, further comprising:

a third input register for storing a programmable value of the first expected result value; and

a fourth input register for storing a programmable value of the second expected result value.

13. The virtual critical path circuit as recited in claim 8, further comprising:

synchronization circuitry defined to synchronize transfer of signals between a domain of the system clock signal and a domain of the special clock signal.

14. A method for real-time system clock optimization, comprising:

operating computational circuitry to compute an output value based on an input value, the computational circuitry operated in accordance with a special clock signal, the computational circuitry having a signal timing characteristic substantially equivalent to a signal timing characteristic of a critical path circuit defined to operate in accordance with a system clock signal, the special clock signal generated separate from the system clock signal, the computational circuitry operated independent from the critical path circuit;

comparing the output value with an expected result value to determine if the output value is correct, wherein a correct output value indicates that a frequency of the special clock signal is acceptable, and wherein an incorrect output value indicates that the frequency of the special clock signal is not acceptable; and

adjusting a frequency of the system clock signal to match an acceptable frequency of the special clock signal.

15. The method for real-time system clock optimization as recited in claim 14, further comprising:

increasing a frequency of the special clock signal for successive operation of the computation circuitry to compute the output value based on the input value and comparison of the output value with the expected result value, the frequency of the special clock signal increased to determine a maximum acceptable frequency of the special clock signal, wherein the maximum acceptable frequency of the special clock signal is a largest frequency of the special clock signal that provides for correct computation of the output value by the computational circuitry based on comparison of the output value with the expected result value.

16. The method for real-time system clock optimization as recited in claim 15, further comprising:

alternating between a first input value and a second input value between successive cycles of the special clock signal, and alternating between a first expected result value and a second expected result value between successive cycles of the special clock signal, such that the first input value and the first expected result value are used on a same cycle of the special clock signal and such that the second input value and the second expected result value are used on a same cycle of the special clock signal.

17. The method for real-time system clock optimization as recited in claim 16, further comprising:

upon determining the maximum acceptable frequency of the special clock signal, adjusting the frequency of the system clock signal to match the maximum acceptable frequency of the special clock signal.

18. The method for real-time system clock optimization as recited in claim 17, further comprising:

synchronizing transfer of signals between a domain of the system clock signal and a domain of the special clock signal.

19. The method for real-time system clock optimization as recited in claim 16, further comprising:

loading the first input value, the second input value, the first expected result value, and the second expected result value into registers for access in operating the computational circuitry to compute the output value based on the input value and for access in comparing the output value with the expected result value.

20. The method for real-time system clock optimization as recited in claim 14, wherein the computational circuitry is located near the critical path circuit on a semiconductor chip such that the computational circuitry and the critical path circuit are subject to similar process variation during manufacture, and such that the computational circuitry and the critical path circuit are subject to similar voltage and temperature during operation of the semiconductor chip.