METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR STORAGE SYSTEM

• US 20150255159A1
• Filed: 03/10/2015
• Published: 09/10/2015
• Est. Priority Date: 04/02/2007
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TANAKA, Yoshiyuki
• Application Number:
  US14/643,818
• Publication Number:
  US 20150255159A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A semiconductor storage system includes a first memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing n bits data, the block is a minimum unit which is capable of being independently erased, a second memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing m (m>n: m is integer) bits data, the block is a minimum unit which is capable of being independently erased, and a controller which controls a number of rewrites for the block in the first memory region not to be more than first predetermined number of times, and controls a number of rewrites for the block in the second memory region not to be more than a second predetermined number of times.

Claims

1. A semiconductor storage system comprising:

a first memory region including at least one block constituted from a plurality of memory cells, the memory cell being capable of storing bits data, the block being a minimum unit which is capable of being independently erased;

a second memory region including at least one block constituted from a plurality of memory cells, the memory cell being capable of storing m (m>

n;

m is integer) bit data, the block being a minimum unit which is capable of being independently erased; and

a controller which controls a number of rewrites for the block in the first memory region not to be more than a first predetermined number of times, and controls a number of rewrites for the block in the second memory region not to be more than a second predetermined number of times.