REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

• US 20150255458A1
• Filed: 03/06/2014
• Published: 09/10/2015
• Est. Priority Date: 03/06/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ando, Takashi, Faltermeier, Johnathan E., Fan, Su Chen, Kanakasabapathy, Sivananda K., Yamashita, Tenko, Ok, Injo
• Granted Patent: US 9,312,136 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

Claims

1. A method of forming a semiconductor structure, the method comprising:

depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate, a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess;

depositing a protective layer above the gate dielectric layer, the protective layer substantially filling the recess;

recessing the protective layer selectively to the gate dielectric layer, wherein a top surface of the protective layer is below of the recess;

recessing the first portion of the gate dielectric layer until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer, wherein the protective layer protects the second portion of the gate dielectric layer while recessing the first portion of the gate dielectric layer;

removing the protective layer;

depositing a conductive barrier above the recessed first portion of the gate dielectric layer;

depositing a metal gate above the conductive barrier; and

forming a capping layer above the metal gate, wherein the conductive barrier separates the capping layer from the recessed first portion of the gate dielectric layer.

2. The method of claim 1, further comprising:

depositing a sacrificial layer above the gate dielectric layer prior to depositing the protective layer;

recessing the sacrificial layer while recessing the first portion of the gate dielectric layer until a top portion of the sacrificial layer is approximately coplanar with the top surface of the protective layer;

protecting the gate dielectric layer with the sacrificial layer while removing the protective layer; and

removing the sacrificial layer prior to depositing the conductive barrier.

3. The method of claim 1, wherein a length of the gate structure is equal or less than 20 nm.

4. The method of claim 1, wherein depositing the protective layer comprises depositing an organic spin material.

5. The method of claim 1, wherein recessing the protective layer comprises forming an etch stop indicator for the recessing of the first portion of the gate dielectric layer.

6. The method of claim 5, wherein recessing the protective layer comprises recessing the protective layer until the protective layer has a thickness ranging from approximately 1 nm to approximately 100 nm.

7. The method of claim 1, wherein depositing the conductive barrier comprises depositing an n-type workfunction metal on the recessed gate dielectric layer.

8. The method of claim 1, wherein depositing a conductive barrier above the recessed first portion of the gate dielectric layer comprises depositing a conductive barrier above the recessed first portion of the gate dielectric layer to prevent diffusion of oxygen atoms and hydroxide ions from the capping layer to the gate dielectric layer.

9. A semiconductor structure, the structure comprising:

a gate structure formed above a substrate, the gate structure comprising;

a metal gate above a conductive barrier, and

a gate dielectric layer below the conductive barrier; and

a capping layer above the gate structure, wherein the conductive barrier separates the capping layer from the gate dielectric layer.

10. The semiconductor structure of claim 9, wherein the gate structure comprises a length less than 20 nm.

11. The semiconductor structure of claim 9, wherein the conductive barrier comprises an n-type workfunction metal.

12. The semiconductor structure of claim 9, wherein the gate dielectric layer comprises a high-k dielectric material such as hafnium oxide.

13. The semiconductor structure of claim 9, wherein the gate dielectric layer has a vertical portion and a horizontal portion, the vertical portion of the gate dielectric having a height less than a height of the metal gate measured from a top surface of the substrate.

14. The semiconductor structure of claim 13, wherein the height of the vertical portion of the gate dielectric of ranges from approximately 1 nm to approximately 100 nm.

15. A semiconductor structure, the structure comprising:

a first gate structure and a second gate structure, wherein a length of the second gate structure is greater than a length of the first gate structure; and

a capping layer above the first gate structure and the second gate structure, wherein

the first gate structure comprises a first metal gate above a first conductive barrier, and a first gate dielectric layer below the first conductive barrier, wherein the first conductive barrier separates the capping layer from the first gate dielectric layer; and

wherein

the second gate structure comprises a second metal gate above a second conductive barrier, and a second gate dielectric layer below the first conductive barrier, wherein the capping layer is in contact with the second gate dielectric layer.

16. The semiconductor structure of claim 15, wherein the first gate structure comprises a length less than 20 nm and the second gate structure comprises a length greater than 50 nm.

17. The semiconductor structure of claim 15, wherein the first conductive barrier and the second conductive barrier comprise an n-type workfunction metal.

18. The semiconductor structure of claim 15, wherein the first gate dielectric layer and the second gate dielectric layer comprise a high-k dielectric material such as hafnium oxide.

19. The semiconductor structure of claim 15, wherein the first gate dielectric layer has a vertical portion and a horizontal portion, the vertical portion of the first gate dielectric layer having a height less than a height of the first metal gate, measured from a top surface of the substrate.

20. The semiconductor structure of claim 15, wherein the second gate dielectric layer has a vertical portion and a horizontal portion, the vertical portion of the second gate dielectric layer having a height approximately equal to the second metal gate, measured from a top surface of the substrate.