COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR STRUCTURE WITH III-V AND SILICON GERMANIUM TRANSISTORS ON INSULATOR

• US 20150255460A1
• Filed: 03/06/2014
• Published: 09/10/2015
• Est. Priority Date: 03/06/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Cheng-wei, Majumdar, Amlan, Shiu, Kuen-Ting
• Granted Patent: US 9,123,569 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate

Abstract

Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET.

Claims

1. A CMOS structure comprising:

a NFET, formed on a wafer, having a gate stack and a channel;

a PFET, formed on the wafer, having a gate stack and a channel;

wherein the channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material;

wherein there is a height difference between a terminal of the NFET and a terminal of the PFET; and

the gate stack NFET is the same height as the gate stack PFET.

2. The CMOS structure of claim 1, wherein the NFET channel and/or the PFET channel has a thickness of 10 nm or less.

3. The CMOS structure of claim 1, wherein the terminal of the NFET includes III-V semiconductor material.

4. The CMOS structure of claim 1, wherein the III-V semiconductor material is InGaAs with low In content.

5. The CMOS structure of claim 1, wherein the valence band offset is about 0.5 eV or less.

6. The CMOS structure of claim 1, wherein the PFET channel includes SiGe or Ge.

7. The CMOS structure of claim 1, wherein the height difference between the terminal of the NFET and the terminal of the PFET is a thickness of the channel of the PFET.

8. The CMOS structure of claim 1, wherein the NFET and/or PFET include a raised source/drain structure.

9. The CMOS structure of claim 1, wherein the wafer is a III-V on insulator wafer.

10. The CMOS structure of claim 1, wherein the terminals of the PFET include Ge.

11. A method of fabricating a CMOS structure on a wafer, the method comprising:

forming, on the wafer, a NFET having a gate stack and a channel;

forming a PFET having a gate stack and a channel;

wherein the channel of the PFET and the channel of the NFET include a semiconductor material formed on a III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide layer because of a valence band offset between the semiconductor material and the III-V semiconductor material;

wherein there is a height difference between a terminal of the NFET and a terminal of the PFET; and

the NFET gate stack is the same height as the PFET gate stack.

12. The method of claim 11, wherein the NFET channel and/or the PFET channel has a thickness of 10 nm or less.

13. The method of claim 11, wherein the terminal of the NFET includes III-V semiconductor material.

14. The method of claim 11, wherein the III-V semiconductor material is InGaAs with low In content.

15. The method of claim 11, wherein the valence band offset is about 0.5 eV or less.

16. The method of claim 11, wherein the PFET channel includes SiGe or Ge.

17. The method of claim 11, wherein the height difference between the terminal of the NFET and the terminal of the PFET is a thickness of the channel of the PFET.

18. The method of claim 11, wherein the NFET and/or PFET include a raised source/drain structure.

19. The method of claim 11, wherein the wafer is a III-V on insulator wafer.

20. The method of claim 11, wherein the terminals of the PFET include Ge.