SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT

• US 20150255556A1
• Filed: 03/05/2014
• Published: 09/10/2015
• Est. Priority Date: 03/05/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Reznicek, Alexander, Surisetty, Charan V. V. S.
• Granted Patent: US 9,293,576 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption.

Claims

1. A semiconductor device fabrication process comprising:

forming at least one gate upon a semiconductor substrate;

forming a first gate cap upon the gate;

forming a contact trench self aligned to the gate, and;

forming a self-aligned contact by filling the contact trench with electrically conductive material, and

subsequent to forming the self aligned contact trench and prior to forming the self-aligned contact, forming a low-k gate cap upon the first gate cap.

2. The semiconductor device fabrication process of claim 1, further comprising:

forming a first interlayer dielectric layer upon the semiconductor substrate so that an upper surface of the first interlayer dielectric layer is coplanar with an upper surface of the first gate cap.

3. The semiconductor device fabrication process of claim 2, further comprising:

forming a sacrificial gate cap upon the gate first gate cap.

4. The semiconductor device fabrication process of claim 3, further comprising:

forming a second interlayer dielectric layer upon the first interlayer dielectric layer surrounding the sacrificial gate cap.

5. The semiconductor device fabrication process of claim 4, further comprising:

subsequent to forming the self aligned contact trench and prior to forming the self-aligned contact, forming a cavity within the contact trench by removing the sacrificial gate cap.

6. The semiconductor device fabrication process of claim 5, further comprising:

prior to forming the self-aligned contact, forming a low-k material layer upon sidewalls of the contact trench and within the cavity.

7. The semiconductor device fabrication process of claim 6, further comprising:

removing the low-k material layer generally formed outside of the cavity.

8. (canceled)

9. The semiconductor device fabrication process of claim 8, wherein the first gate cap and the low-k gate cap form a multilayered gate cap that electrically isolates the gate from the self-aligned contact.

10-20. -20. (canceled)