SOFT DECODING OF POLAR CODES

• US 20150256196A1
• Filed: 03/19/2014
• Published: 09/10/2015
• Est. Priority Date: 03/06/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Alhussien, AbdelHakim S., Haratsch, Erich F., Li, Yue
• Granted Patent: US 9,317,365 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/453 wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Abstract

An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.

Claims

1. An apparatus comprising:

an interface to a nonvolatile memory; and

a circuit configured to (i) read a plurality of bits in a read channel of said nonvolatile memory, wherein said bits are encoded with a polar code, (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of said read channel and (iii) decode said bits based on said probabilities.

2. The apparatus according to claim 1, wherein said circuit is further configured to modify said bits based on said log likelihood ratio values prior to said decoding.

3. The apparatus according to claim 2, wherein (i) a given one of said bits is modified to a logical one value where a corresponding one of said log likelihood ratio values is greater than zero and (ii) said given bit is modified to a logical zero value where said corresponding log likelihood ratio value is less than zero.

4. The apparatus according to claim 1, wherein said probabilities are transition error probabilities of a binary symmetric channel.

5. The apparatus according to claim 1, wherein (i) a given one of said probabilities is generated with a reliable value where a magnitude of a corresponding one of said log likelihood ratio values is large and (ii) said given probability is generated with an unreliable value where said magnitude of said corresponding log likelihood ratio value is small.

6. The apparatus according to claim 1, wherein said decoding is a list polar decoding.

7. The apparatus according to claim 1, wherein two or more of said bits have different channel models.

8. The apparatus according to claim 1, wherein said nonvolatile memory is a flash memory.

9. The apparatus according to claim 1, wherein said apparatus is implemented as one or more integrated circuits.

10. A method for soft decoding of a polar code, comprising the steps of:

(A) reading a plurality of bits in a read channel of a nonvolatile memory, wherein said bits are encoded with said polar code;

(B) generating a plurality of probabilities based on a plurality of log likelihood ratio values of said read channel; and

(C) decoding said bits based on said probabilities.

11. The method according to claim 10, further comprising the step of:

modifying said bits based on said log likelihood ratio values prior to said decoding.

12. The method according to claim 11, wherein (i) a given one of said bits is modified to a logical one value where a corresponding one of said log likelihood ratio values is greater than zero and (ii) said given bit is modified to a logical zero value where said corresponding log likelihood ratio value is less than zero.

13. The method according to claim 10, wherein said probabilities are transition error probabilities of a binary symmetric channel.

14. The method according to claim 10, wherein (i) a given one of said probabilities is generated with a reliable value where a magnitude of a corresponding one of said log likelihood ratio values is large and (ii) said given probability is generated with an unreliable value where said magnitude of said corresponding log likelihood ratio value is small.

15. The method according to claim 10, wherein said decoding is a list polar decoding.

16. The method according to claim 10, wherein two or more of said bits have different channel models.

17. The method according to claim 10, wherein said nonvolatile memory is a flash memory.

18. An apparatus comprising:

means for reading a plurality of bits in a read channel of a nonvolatile memory, wherein said bits are encoded with a polar code;

means for generating a plurality of probabilities based on a plurality of log likelihood ratio values of said read channel; and

means for decoding said bits based on said probabilities.