TIMING CIRCUITS AND DRIVING CIRCUITS USED IN LIGHTING SYSTEMS

• US 20150257219A1
• Filed: 03/10/2015
• Published: 09/10/2015
• Est. Priority Date: 03/10/2014
• Status: Active Grant

• Current Assignee: Chengdu Monolithic Power Systems Company Limited (Monolithic Power Systems Incorporated)
• Original Assignee: Chengdu Monolithic Power Systems Company Limited (Monolithic Power Systems Incorporated)
• Inventors: Chen, Yuedong, Feng, Lin
• Granted Patent: US 9,420,648 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 21/026 comprising logic circuits
• CPC Class Codes: H05B 47/16 by timing means
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
• CPC Class Codes: Y02B 20/40 Control techniques providing energy savings, e.g. smart controller or presence detection

Abstract

A timing circuit used in lighting systems includes a first logic circuit, a first counter, a latching circuit and a judging circuit. The first logic circuit generates a first logic signal and a second logic signal based on a falling edge of a detecting signal. The first counter generates a first counting signal and a second counting signal based on the second logic signal, wherein the counting period of the first counting signal is longer than that of the second counting signal. The latching circuit samples and holds the first counting signal based on the first logic signal and provides a third counting signal. The judging circuit detects whether the second counting signal is equal to the third counting signal and provides a timing signal.

Claims

1. A timing circuit, comprising:

a first logic circuit having an input terminal, a first output terminal and a second output terminal, wherein the input terminal is configured to receive a detecting signal, and wherein based on a falling edge of the detecting signal, the first logic circuit provides a first logic signal and a second logic signal at the first output terminal and the second output terminal respectively;

a first counter having a control terminal, a first output terminal and a second output terminal, wherein the control terminal is coupled to the second output terminal of the first logic circuit for receiving the second logic signal, and wherein based on the second logic signal, the first counter generates a first counting signal at the first output terminal and a second counting signal at the second output terminal, and wherein a counting period of the first counting signal is longer than a counting period of the second counting signal;

a latching circuit having a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the first output terminal of the first logic circuit for receiving the first logic signal, and wherein the input terminal is coupled to the first output terminal of the first counter for receiving the first counting signal, and wherein based on the first logic signal, the latching circuit samples and holds the first counting signal and provides a third counting signal at the output terminal; and

a judging circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second output terminal of the first counter for receiving the second counting signal, the second input terminal is coupled to the output terminal of the latching circuit for receiving the third counting signal, and wherein the judging circuit detects whether the second counting signal is equal to the third counting signal and provides a timing signal at the output terminal accordingly.

2. The timing circuit of claim 1, wherein the first logic signal and the second logic signal are the same.

3. The timing circuit of claim 1, wherein the first logic signal and the detecting signal are the same.

4. The timing circuit of claim 1, wherein the latching circuit samples and holds the first counting signal for a first time period from a falling edge of the detecting signal, and wherein the first counter starts to count for a second time period from the falling edge of the detecting signal, and wherein the second time period is longer than the first time period.

5. The timing circuit of claim 4, wherein the first time period is zero.

6. The timing circuit of claim 1, wherein either the first logic signal or the second logic signal is a pulse signal.

7. The timing circuit of claim 1, wherein the first counter comprises N terminals configured to provide an N-bit digital signal, and wherein the first counting signal is comprised of the high N−

M bits of the N-bit digital signal, the second counting signal is comprised of the low N−

M bits of the N-bit digital signal, and wherein M is an integer smaller than N.

8. The timing circuit of claim 7, wherein the difference between N and M is 2 or 3.

9. The timing circuit of claim 7, wherein the N-bit digital signal is a binary data with successively-incremented-carry-number.

10. A driving circuit for a lighting system, wherein the lighting system comprises a dimmer, a bridge rectifier and a light emission device, and wherein the driving circuit comprises:

a detecting circuit having an input terminal coupled to an output terminal of the bridge rectifier and an output terminal configured to provide a detecting signal;

a compensating circuit having an input terminal coupled to the output terminal of the detecting circuit and an output terminal configured to provide a compensated detecting signal; and

a control circuit configured to adjust voltage or current of the light emission device based on the compensated detecting signal;

wherein the compensating circuit comprises;

a timing circuit, comprising;

a first logic circuit having an input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the detecting circuit for receiving the detecting signal, and wherein based on a falling edge of the detecting signal, the first logic circuit provides a first logic signal and a second logic signal at the first output terminal and the second output terminal respectively;

a first counter having a control terminal, a first output terminal and a second output terminal, wherein the control terminal is coupled to the second output terminal of the first logic circuit for receiving the second logic signal, and wherein based on the second logic signal, the first counter generates a first counting signal at the first output terminal and a second counting signal at the second output terminal, and wherein a counting period of the first counting signal is longer than a counting period of the second counting signal;

a latching circuit having a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the first output terminal of the first logic circuit for receiving the first logic signal, and wherein the input terminal is coupled to the first output terminal of the first counter for receiving the first counting signal, and wherein based on the first logic signal, the latching circuit samples and holds the first counting signal and provides a third counting signal at the output terminal;

a judging circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second output terminal of the first counter for receiving the second counting signal, the second input terminal is coupled to the output terminal of the latching circuit for receiving the third counting signal, and wherein the judging circuit detects whether the second counting signal is equal to the third counting signal and provides a timing signal at the output terminal; and

an operating circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the detecting circuit for receiving the detecting signal, and wherein the second input terminal is coupled to the output terminal of the timing circuit for receiving the timing signal, and wherein based on the detecting signal and the timing signal, the operating circuit provides the compensated detecting signal at the output terminal.

11. The driving circuit of claim 10, wherein the duty cycle of the detecting signal is increased by a compensation duty cycle determined by the timing signal if the duty cycle of the detecting signal is smaller than a critical duty cycle, and wherein the duty cycle of the detecting signal is increased to a high duty cycle if the duty cycle of the detecting signal is larger than the critical duty cycle.

12. The driving circuit of claim 11, wherein the critical duty cycle is 75%, and the compensation duty cycle is 25%, and the high duty cycle is 100%.

13. The timing circuit of claim 10, wherein the first logic signal and the second logic signal are the same.

14. The driving circuit of claim 10, wherein the first logic signal and the detecting signal are the same.

15. The driving circuit of claim 10, wherein the latching circuit samples and holds the first counting signal for a first time period from a falling edge of the detecting signal, and wherein the first counter starts to count for a second time period from the falling edge of the detecting signal, and wherein the second time period is longer than the first time period.

16. The driving circuit of claim 15, wherein the first time period is zero.

17. The driving circuit of claim 10, wherein the first logic signal or the second logic signal is a pulse signal.

18. The driving circuit of claim 10, wherein the first counter is comprised of N terminals configured to provide a N-bit digital signal, and wherein the first counting signal is comprised of the high N−

M bits of the N-bit digital signal, the second counting signal is comprised of the low N−

M bits of the N-bit digital signal, and wherein M is an integer smaller than N.

19. The driving circuit of claim 18, wherein the difference between N and M is 2 or 3.

20. The driving circuit of claim 18, wherein the N-bit digital signal is a binary data with successively-incremented-carry-number.