Systems and Methods for Messaging-based Fine Granularity System-on-a-Chip Power Gating

• US 20150261290A1
• Filed: 03/11/2014
• Published: 09/17/2015
• Est. Priority Date: 03/11/2014
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Bagheri, Mehran, Gatherer, Alan, Brown, Mark, Yan, Peter
• Granted Patent: US 9,448,617 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.

Claims

1. A method in a first system on a chip (SoC) resource for messaging-based power gating, the method comprising:

receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource;

determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource;

setting a wake-up time timer to expire at the wake-up time; and

waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep, wherein waking up the first SoC resource comprises waking up at least one sub-resource in the first SoC resource.

2. The method of claim 1, further comprising putting the first SoC resource into a sleep state when the first SoC resource is in an idle state and a current wake-up time for which the wake-up time timer is set to expire comprises a greater time duration from a current time than a resource break-even time, wherein the sleep state comprises a low power state for one or more sub-components in the first SoC resource.

3. The method of claim 2, wherein the break-even time comprises a time needed by the first SoC resource to be kept in a powered down state to cover a cost of powering the first SoC resource up.

4. The method of claim 3, wherein the break-even time further comprises an error guardband added to the time needed by the first SoC resource to be kept in a powered down state to cover a cost of powering the first SoC resource up.

5. The method of claim 1, further comprising putting the first SoC resource into a sleep state when the SoC resource is in an idle state when there is no wake-up time scheduled, wherein the sleep state comprises a lower power state for one or more sub-components in the first SoC resource.

6. The method of claim 1, further comprising:

maintaining a wake-up time queue comprising a plurality of wake-up times, wherein the wake-up time queue keeps track of future wake-up times the first SoC resource will need to wake-up; and

setting the wake-up time timer to expire for a one of the plurality of wake-up times that will arrive soonest.

7. The method of claim 1, further comprising:

determining a time period for a process to be completed by the first SoC resource;

determining a third SoC resource to which a second result message generated as a result of completion of the process will be sent;

determining a time to transmit the second result message to the third SoC resource from the first SoC resource; and

sending a second WNM to the third SoC resource, wherein the WNM comprises a second wake-up time, wherein the second wake-up time comprises a time at which the third SoC resource is expected to receive the second result message, and wherein the second wake-up time is determined according to the time period for the process to be completed by the first SoC resource and the time to transmit the second result message to the third SoC resource from the first SoC resource.

8. The method of claim 1, wherein determining the wake-up time according to the time at which the result message from the second SoC is expected to arrive at the first SoC resource comprises determining an amount of time necessary for the first SoC resource to power up and be ready to operate without a latency and setting the wake-up time to a time that is before the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource by at least the amount of time necessary for the first SoC resource to power up and be ready to operate without a latency.

9. A system on a chip (SoC) resource, the SoC resource comprising:

an input/output (I/O) interface connected to an interconnect and configured to receive a wakeup notification message (WNM) from a second SoC resource via the interconnect, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the SoC resource; and

a power management controller coupled to the I/O interface and configured to determine a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the SoC resource, set a wake-up time timer to expire at the wake-up time, and wake up at least one sub-component in the SoC resource when the wake-up time timer expires when the at least one sub-component in the SoC resource is in a sleep state.

10. The SoC resource of claim 9, wherein the power management controller is further configured to put the SoC resource into a sleep state when the SoC resource is in an idle state and a current wake-up time for which the wake-up time timer is set to expire comprises a greater time duration from a current time than a resource break-even time, wherein the sleep state comprises a low power state for one or more sub-components in the SoC resource.

11. The SoC resource of claim 10, wherein the break-even time comprises a time needed by the SoC resource to be kept in a powered down state to cover a cost of powering the SoC resource up.

12. The SoC resource of claim 11, wherein the break-even time further comprises an error guardband added to the time needed by the SoC resource to be kept in a powered down state to cover a cost of powering the SoC resource up.

13. The SoC resource of claim 9, wherein the power management controller is further configured to put the SoC resource into a sleep state when the SoC resource is in an idle state when there is no wake-up time scheduled, wherein the sleep state comprises a lower power state for one or more sub-components in the SoC resource.

14. The SoC resource of claim 9, wherein the power management controller is further configured to:

maintain a wake-up time queue comprising a plurality of wake-up times, wherein the wake-up time queue keeps track of future wake-up times the SoC resource will need to wake-up; and

set the wake-up time timer to expire for a one of the plurality of wake-up times that will arrive soonest.

15. The SoC resource of claim 9, wherein the power management controller is further configured to:

determine a time period for a process to be completed by the SoC resource;

determine a third SoC resource to which a second result message generated as a result of completion of the process will be sent;

determine a time to transmit the second result message to the third SoC resource from the SoC resource; and

cause the I/O interface to send a second WNM to the third SoC resource,

wherein the WNM comprises a second wake-up time, wherein the second wake-up time comprises a time at which the third SoC resource is expected to receive the second result message, and wherein the second wake-up time is determined according to the time period for the process to be completed by the SoC resource and the time to transmit the second result message to the third SoC resource from the SoC resource.

16. The SoC resource of claim 9, wherein the power management controller is configured to determine an amount of time necessary for the SoC resource to power up and be ready to operate without a latency and configured to set the wake-up time to a time that is before the time at which the result message from the second SoC resource is expected to arrive at the SoC resource by at least the amount of time necessary for the SoC resource to power up and be ready to operate without a latency in order to determine the wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the SoC resource.

17. The SoC resource of claim 9, wherein the sleep state comprises one of three sleep modes, wherein the three sleep modes comprise a light sleep mode, a deep sleep mode, and a shut down mode, wherein the light sleep mode comprises a shortest wakeup time and a least power savings of the three sleep modes, wherein the shut down mode comprises a longest wakeup time and a maximum power savings of the three modes, and wherein the deep sleep mode provides a wakeup time and a power savings that are between those provided by the light sleep mode and the deep sleep mode.

18. A data processing system, comprising:

a plurality of system on a chip (SoC) resources configured for messaging based communication with each other; and

a network bus connected to each of the plurality of SoC resources,

wherein at least one of the SoC resources comprises;

an input/output (I/O) interface connected to the network bus;

at least one resource processing sub-component or resource storage sub-component connected to the I/O interface;

a power management controller connected to the I/O interface;

a power supply connected to the power management controller and connected to the at least one resource processing sub-component or resource storage sub-component connected to the I/O interface; and

a wake-up time timer connected to the power management controller,

wherein the I/O interface is configured to receive a wakeup notification message (WNM) from another one of the SoC resources, wherein the WNM comprises a time at which a result message from the another one of the SoC resources is expected to arrive at the at least one of the SoC resources, and

wherein the power management controller is configured to determine a wake-up time according to the time at which the result message from the another one of the SoC resources is expected to arrive at the at least one of the SoC resources, set the wake-up time timer to expire at the wake-up time, and wake up at least one sub-resource in at least one of the SoC resources when the wake-up time timer expires when at least one sub-resource in at least one of the SoC resources is asleep.

19. The data processing system of claim 18, wherein the power management controller is further configured to put the at least one of the SoC resources into a sleep state when the at least one of the SoC resources is in an idle state and a current wake-up time for which the wake-up time timer is set to expire comprises a greater time duration from a current time than a resource break-even time, wherein the sleep state comprises a low power state for the at least one resource processing sub-component or resource storage sub-component.

20. The data processing system of claim 19, wherein the break-even time comprises a time needed by the at least one of the SoC resources to be kept in a powered down state to cover a cost of powering the at least one of the SoC resources up.

21. The data processing system of claim 20, wherein the break-even time further comprises an error guardband added to the time needed by the at least one of the SoC resources to be kept in a powered down state to cover a cost of powering the at least one of the SoC resources up.

22. The data processing system of claim 18, wherein the power management controller is further configured to put the at least one of the SoC resources into a sleep state when the at least one of the SoC resources is in an idle state when there is no wake-up time scheduled, wherein the sleep state comprises a lower power state for the at least one resource processing sub-component or resource storage sub-component.

23. The data processing system of claim 18, wherein the power management controller is further configured to:

maintain a wake-up time queue comprising a plurality of wake-up times, wherein the wake-up time queue keeps track of future wake-up times at which the at least one of the SoC resources will need to wake-up; and

set the wake-up time timer to expire for a one of the plurality of wake-up times that will arrive soonest.

24. The data processing system of claim 18, wherein the power management controller is further configured to:

determine a time period for a process to be completed by the at least one of the SoC resources;

determine a second SoC resource from the SoC resources to which a second result message generated as a result of completion of the process will be sent;

determine a time to transmit the second result message to the second SoC resource from the at least one of the SoC resources; and

send a second WNM to the second SoC resource, wherein the second WNM comprises a second wake-up time, wherein the second wake-up time comprises a time at which the second SoC resource is expected to receive the second result message, and wherein the second wake-up time is determined according to the time period for the process to be completed by the at least one of the SoC resources and the time to transmit the second result message to the second SoC resource from the at least one of the SoC resources.

25. The data processing system of claim 18, wherein the power management controller is further configured to determine the wake-up time according to the time at which the result message from the other SoC resource is expected to arrive at the at least one of the SoC resources according to an amount of time necessary for the at least one of the SoC resources to power up and be ready to operate without a latency and to set the wake-up time to a time that is before the time at which the result message from the other SoC resource is expected to arrive at the at least one of the SoC resources by at least the amount of time necessary for the at least one of the SoC resources to power up and be ready to operate without a latency.

26. The data processing system of claim 18, wherein the network bus comprises one of a network on a chip (NoC) and a cross bar interconnect.