CONFIGURABLE READ-MODIFY-WRITE ENGINE AND METHOD FOR OPERATING THE SAME IN A SOLID STATE DRIVE

• US 20150261456A1
• Filed: 03/13/2014
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: NGD Systems, Inc.
• Original Assignee: NxGn Data, Inc.
• Inventors: Alcantara, Joao, Alves, Vladimir
• Granted Patent: US 9,448,745 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2211/007 Encryption, En-/decode, En-/decipher, En-/decypher, Scramble, (De-)compress
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A method of writing host data to a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method including receiving a command from the CPU to write the host data to a location in the non-volatile memory, the host data being associated with a first plurality of codewords (CWs), allocating space in a buffer memory of the FRB for storage of the first CWs, storing the first CWs into the allocated space in the buffer memory, extracting data from the stored first CWs, organizing the extracted data and the host data into a second plurality of CWs, transferring a second CWs to a physical addresses in the non-volatile memory, and sending the plurality of physical addresses to the CPU to update a logical-to-physical table.

Claims

1. A method of writing host data to a storage device comprising a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method comprising:

receiving, by the FRB, a command from the CPU to write the host data to a location in the non-volatile memory, the host data being associated with a first plurality of codewords (CWs);

allocating space, by the FRB, in a buffer memory of the FRB for storage of the first plurality of CWs;

storing, by the FRB, the first plurality of CWs into the allocated space in the buffer memory;

extracting, by the FRB, data from the stored first plurality of CWs;

organizing, by the FRB, the extracted data and the host data into a second plurality of CWs;

transferring, by the FRB, a second plurality of CWs to a plurality of physical addresses in the non-volatile memory; and

sending, by the FRB, the plurality of physical addresses to the CPU to update a logical-to-physical table.

2. The method of claim 1, wherein the host data corresponds to one or more CWs that are adjacent to the first plurality of CWs.

3. The method of claim 1,

wherein the buffer memory comprises a plurality of codeword (CW) spaces, each CW space of the plurality of CW spaces being associated with a CW index of a plurality of CW indexes, the CW indexes being stored in a CW pool of the FRB, and

wherein the allocating of the space in the buffer memory comprises:

determining, by the FRB, a count N of at least one of the first plurality of CWs and CW spaces sufficient to store the host data in the buffer memory;

retrieving, by the FRB, N CW indexes from the CW pool on a first-in-first-out basis; and

removing, by the FRB, the N CW indexes from the CW pool.

4. The method of claim 3, wherein the storing of the first plurality of CWs comprises storing the first plurality of CWs into N CW spaces of the buffer memory that are associated with the retrieved N CW indexes.

5. The method of claim 3, further comprising de-allocating, by the FRB, the allocated space in the buffer memory.

6. The method of claim 5, wherein the de-allocating of the allocated space in the buffer memory comprises adding, by the FRB, the removed N CW indexes to the CW pool.

7. The method of claim 1, wherein the extracting of the data from the stored first plurality of CWs comprises:

instructing, by the FRB, an error correction code (ECC) engine to decode the first plurality of CWs and to generate a first plurality of payload sections and a corresponding first plurality of parity sections;

receiving, by the FRB, the first plurality of payload sections; and

combining, by the FRB, the first plurality of payload sections to recreate the data,

wherein bits of the first plurality of payload sections are corrected by the ECC engine based on the corresponding first plurality of parity sections.

8. The method of claim 1, wherein the organizing of the data into a second plurality of CWs comprises:

receiving, by the FRB, the host data from a path controller of the storage device;

organizing, by the FRB, the host data and the extracted data in a sequence to generate a data block;

encoding, by the FRB, the data block into the second plurality of CWs.

9. The method of claim 1, wherein the organizing of the data into a second plurality of CWs comprises:

sending, by the FRB, the extracted data to a path controller of the storage device;

receiving, by the FRB, a command from the CPU to write a data block to the non-volatile memory, the data block comprising the extracted data and the host data;

receiving, by the FRB, the data block from the path controller;

encoding, by the FRB, the data block into the second plurality of CWs,

wherein the path controller organizes the host data and the extracted data in a sequence to generate the data block.

10. The method of claim 9, wherein the encoding of the data block comprises:

dividing, by the FRB, the data block into a second plurality of payload sections; and

instructing, by the FRB, an ECC engine to encode the second plurality of payload sections and to generate a second plurality of parity sections;

receiving, by the FRB, the second plurality of parity sections from the ECC engine, each parity section of the second plurality of parity sections corresponding to a payload section of the second plurality of payload sections; and

combining, by the FRB, each payload section of the second plurality of payload sections with the corresponding one of the second plurality of parity sections to generate the second plurality of CWs.

11. The method of claim 10, wherein each parity section of the second plurality of parity sections comprises one or more parity bits.

12. The method of claim 10, wherein the FRB varies a size of each payload section of the second plurality of payload sections and instructs the ECC engine to vary a size of each parity section of the second plurality of parity sections.

13. The method of claim 1, wherein the transferring of the second plurality of CWs comprises writing the second plurality of CWs to memory dies of the non-volatile memory that are not marked as invalid by the CPU.

14. A storage device configured to receive and store host data in response to a host write request, the storage device comprising a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the FRB comprising:

a processor; and

a memory having stored thereon instructions that, when executed by the processor, cause the processor to perform;

receiving a command from the CPU to write the host data to a location in the non-volatile memory, the host data being associated with a first plurality of codewords (CWs);

allocating space in a buffer memory of the FRB for storage of the first plurality of CWs;

storing the first plurality of CWs into the allocated space in the buffer memory;

extracting data from the stored first plurality of CWs;

organizing the extracted data and the host data into a second plurality of CWs;

transferring a second plurality of CWs to a plurality of physical addresses in the non-volatile memory; and

sending the plurality of physical addresses to the CPU to update a logical-to-physical table.

15. The storage device of claim 14,

wherein the buffer memory comprises a plurality of codeword (CW) spaces, each CW space of the plurality of CW spaces being associated with a CW index of a plurality of CW indexes, the CW indexes being stored in a CW pool of the FRB, and

wherein the allocating of the space in the buffer memory comprises:

determining a count N of at least one of the first plurality of CWs and CW spaces sufficient to store the host data in the buffer memory;

retrieving N CW indexes from the CW pool on a first-in-first-out basis; and

removing the N CW indexes from the CW pool.

16. The storage device of claim 15, wherein the storing of the first plurality of CWs comprises storing the first plurality of CWs into N CW spaces of the buffer memory that are associated with the retrieved N CW indexes.

17. The storage device of claim 14, wherein the extracting of the data from the stored first plurality of CWs comprises:

instructing an error correction code (ECC) engine to decode the first plurality of CWs and to generate a first plurality of payload sections and a corresponding first plurality of parity sections;

receiving the first plurality of payload sections; and

combining the first plurality of payload sections to recreate the data,

wherein bits of the first plurality of payload sections are corrected by the ECC engine based on the corresponding first plurality of parity sections.

18. The storage device of claim 14, wherein the organizing of the data into a second plurality of CWs comprises:

receiving the host data from a path controller of the storage device;

organizing the host data and the extracted data in a sequence to generate a data block;

encoding the data block into the second plurality of CWs.

19. The storage device of claim 14, wherein the organizing of the data into a second plurality of CWs comprises:

sending the extracted data to a path controller of the storage device;

receiving a command from the CPU to write a data block to the non-volatile memory, the data block comprising the extracted data and the host data;

receiving the data block from the path controller;

encoding the data block into the second plurality of CWs,

wherein the path controller organizes the host data and the extracted data in a sequence to generate the data block.

20. The storage device of claim 19, wherein the encoding of the data block comprises:

dividing the data block into a second plurality of payload sections; and

instructing an ECC engine to encode the second plurality of payload sections and to generate a second plurality of parity sections;

receiving the second plurality of parity sections from the ECC engine, each parity section of the second plurality of parity sections corresponding to a payload section of the second plurality of payload sections; and

combining each payload section of the second plurality of payload sections with the corresponding one of the second plurality of parity sections to generate the second plurality of CWs.