COMPUTER ACCELERATOR SYSTEM WITH IMPROVED EFFICIENCY

• US 20150261528A1
• Filed: 03/14/2014
• Published: 09/17/2015
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Ho, Chen-Han, Sankaralingam, Karthikeyan, Kim, Sung
• Granted Patent: US 10,591,983 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption.

Claims

1. A computer comprising:

a first processor communicating with an external memory and including circuitry to provide execution of a first set of standard computer instructions and circuitry for an exchange of data with the external memory;

a second processor communicating with the first processor including circuitry to provide execution of a second set of accelerator computer instructions providing the execution of functions at an accelerated rate compared to the execution of those functions on the first processor; and

a third processor communicating with the first processor and the second processor and including circuitry to provide for the execution of a third set of memory access instructions, the third processor operating to receive the memory access instructions from the first processor to exchange data between the second processor and external memory via the third processor according to those memory access instructions during operation of the second processor.

2. The computer of claim 1 wherein the circuitry of the third processor executing the third set of memory access instructions provides for the exchange of data between the second processor and external memory via the third processor using less power than required for the exchange of data between the second processor and external memory via the first processor.

3. The computer of claim 2 wherein the first processor is an out-of-order processor speculatively executing instructions out of program order.

4. The computer of claim 3 wherein the third processor employs a trigger architecture for sequencing through the third set of memory access instructions without a program counter.

5. The computer of claim 4 wherein the third set of memory access instructions includes a list of trigger events and responses, where the trigger events include an availability of data from the accelerator or memory and the responses include moving data between the accelerator and external memory.

6. The computer of claim 1 wherein the third set of memory access instructions includes a data flow fabric configuration for calculating addresses in the external memory.

7. The computer of claim 1 wherein the first processor provides the second set of accelerator computer instructions to the second processor.

8. The computer of claim 1 wherein the computer shuts down the first processor during operation of the third processor.

9. The computer of claim 1 wherein the second processor does not include circuitry for the exchange of data with the external memory.

10. The computer of claim 1 wherein the first processor provides initial memory access data to the third processor.

11. The computer of claim 1 wherein the third set of memory access instructions is limited to those needed to provide iterative calculation of memory addresses in a predictable pattern of offsets starting with an initial memory access data provided from the first processor.

12. The computer of claim 1 wherein the second processor is selected from the group consisting of an arithmetic coprocessor, a graphic coprocessor, a streaming processor, and a neural net processor.

13. The computer of claim 1 wherein the first processor sends memory access instructions to the third processor based on compiler-generated instructions in a program executed by the first processor.

14. A method of executing a program using a computer having:

a first processor communicating with an external memory and including circuitry to provide execution of a first set of standard computer instructions and circuitry for an exchange of data with the external memory;

a second processor communicating with the first processor including circuitry to provide execution of a second set of accelerator computer instructions providing the execution of functions at an accelerated rate compared to the execution of those functions on the first processor; and

a third processor communicating with the first processor and the second processor and including circuitry to provide for the execution of a third set of memory access instructions, the third processor receiving the memory access instructions from the first processor to exchange data between the second processor and external memory via the third processor according to those memory access instructions during operation of the second processor;

the method comprising the steps of;

(a) executing a program by the first processor to a beginning of an acceleration region of the program where faster execution could be provided by the second processor;

(b) providing memory access instructions to the third processor for accessing memory for the second processor for execution of the acceleration region; and

(c) executing the acceleration region by the second and third processor and not by the first processor.

15. The method of claim 14 wherein during step (c) the first processor is operated in a reduced power mode consuming less power than in step (a).

16. The method of claim 14 including the step of the first processor providing the second set of accelerator computer instructions to the second processor.

17. The method of claim 14 wherein the second processor does not access the external memory except via the third processor.

18. The method of claim 14 including the step of the first processor providing initial memory access data to the third processor.

19. The method of claim 14 wherein the first processor speculatively executes instructions of the program before the acceleration region out of program order.

20. The method of claim 14 wherein the second processor provides instructions limited to three primitive tasks of:

(i) computation to generate recurring address patterns/branches;

(ii) managing and triggering recurring events related to an arrival of values from memory or the second processor; and

(iii) moving information between memory and the second processor.