DYNAMIC STORAGE KEY ASSIGNMENT

• US 20150261693A1
• Filed: 03/14/2014
• Published: 09/17/2015
• Est. Priority Date: 03/14/2014
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craddock, David F., Gregg, Thomas A.
• Application Number:
  US14/211,168
• Publication Number:
  US 20150261693A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/303 In peripheral interface, e.g. I/O adapter or channel
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0637 Permissions
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A dynamic storage key assignment is provided. An aspect includes receiving, by a host bridge, a request. An aspect includes determining, by the host bridge, that a dynamic storage key assignment is supported and enabled in association with a memory address space referenced by the request based on a requester identifier or a portion of a peripheral component interconnect address associated with the request. An aspect includes, based on determining that the dynamic storage key assignment is supported and enabled, accessing, by the host bridge, a page included in the memory address space based on a storage key included in the request matching a storage key associated with the page being accessed or an entry in a listing of permitted storage keys for the memory address space.

Claims

1. A computer implemented method for a dynamic storage key assignment, the method comprising:

receiving, by a host bridge, a request;

determining, by the host bridge, that a dynamic storage key assignment is supported and enabled in association with a memory address space referenced by the request based on a requester identifier or a portion of a peripheral component interconnect address associated with the request; and

based on determining that the dynamic storage key assignment is supported and enabled, accessing, by the host bridge, a page included in the memory address space based on a storage key included in the request matching a storage key associated with the page being accessed or an entry in a listing of permitted storage keys for the memory address space.

2. The method of claim 1, further comprising:

determining, by the host bridge, that the dynamic storage key assignment is supported and enabled based on one or more control mode indicators associated with the memory address space.

3. The method of claim 1, further comprising:

determining, by the host bridge, that the access to the memory address space referenced by the request is authorized based on determining that access controls within a device table entry permit access.

4. The method of claim 1, wherein the request is forwarded by a switch associated with a peripheral component interconnect adapter.

5. The method of claim 1, wherein the access of the page included in the memory address space is based on an entry stored in a cache.

6. The method of claim 1, wherein the access of the page included in the memory address space is associated with at least one of:

a read operation, a write operation, and an atomic operation with respect to the page.

7. The method of claim 1, wherein the storage key included in the request corresponds to a redefinition of one or more peripheral component interconnect address bits.

8. A computer program product for a dynamic storage key assignment, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving, by a host bridge, a request;

determining, by the host bridge, that a dynamic storage key assignment is supported and enabled in association with a memory address space referenced by the request based on a requester identifier or a portion of a peripheral component interconnect address associated with the request; and

based on determining that the dynamic storage key assignment is supported and enabled, accessing, by the host bridge, a page included in the memory address space based on a storage key included in the request matching a storage key associated with the page being access or an entry in a listing of permitted storage keys for the memory address space.

9. The computer program product of claim 8, wherein the method performed by the processing circuit further comprises:

determining, by the host bridge, that the dynamic storage key assignment is supported and enabled based on one or more control mode indicators associated with the memory address space.

10. The computer program product of claim 8, wherein the method performed by the processing circuit further comprises:

determining, by the host bridge, that the access to the memory address space referenced by the request is authorized based on determining that access controls within a device table entry permit access.

11. The computer program product of claim 8, wherein the method performed by the processing circuit further comprises:

receiving, by the host bridge, the request from a switch associated with a peripheral component interconnect adapter.

12. The computer program product of claim 8, wherein the method performed by the processing circuit further comprises:

accessing, by the host bridge, the page included in the memory address space based on determining that an entry associated with the page included in the memory address space is stored in a cache.

13. The computer program product of claim 8, wherein the access of the page included in the memory address space is associated with a read operation with respect to the page.

14. The computer program product of claim 8, wherein the access of the page included in the memory address space is associated with a write operation with respect to the page.

15. The computer program product of claim 8, wherein the storage key included in the request corresponds to a redefinition of one or more address bits.

16. A computer system for a dynamic storage key assignment, the system comprising:

a memory having computer readable instructions; and

a processor configured to execute the computer readable instructions, the instructions comprising;

receiving a request;

determining that a dynamic storage key assignment is supported and enabled in association with a memory address space referenced by the request based on a requester identifier or a portion of a peripheral component interconnect address associated with the request; and

based on determining that the dynamic storage key assignment is supported and enabled, accessing a page included in the memory address space based on a storage key included in the request matching a storage key associated with the page being accessed or an entry in a listing of permitted storage keys for the address space.

17. The computer system of claim 16, wherein the instructions comprise:

determining that the dynamic storage key assignment is supported and enabled based on one or more control mode indicators associated with the memory address space.

18. The computer system of claim 16, wherein the instructions comprise:

determining that the access to the memory address space referenced by the request is authorized based on determining that access controls within a device table entry permit access.

19. The computer system of claim 16, wherein the instructions comprise:

receiving the request from a switch associated with a peripheral component interconnect adapter.

20. The computer system of claim 16, wherein the memory address space is a direct memory access address space, and wherein the instructions comprise:

translating an address included in the request in accessing the page.