DEVICE TABLE IN SYSTEM MEMORY

• US 20150261701A1
• Filed: 03/14/2014
• Published: 09/17/2015
• Est. Priority Date: 03/14/2014
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craddock, David F., Gregg, Thomas A., Lais, Eric N.
• Application Number:
  US14/211,425
• Publication Number:
  US 20150261701A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements

Abstract

Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. An aspect includes an access of the device table in the system memory by a switch coupled to the host bridge, management of a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes and maintenance of a usage count and an in-use count in the host bridge for each cached DTE.

Claims

1. A method for implementing a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge, the method comprising:

accessing the device table in the system memory by the host bridge;

managing a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes; and

maintaining a usage count and an in-use count in the host bridge for each cached DTE.

2. The method according to claim 1, wherein the device table in the system memory has at least 3 orders of magnitude more entries than the DTE cache.

3. The method according to claim 1, further comprising accessing the DTE cache for DMA operations.

4. The method according to claim 1, wherein, for a PCI instruction, the method further comprises updating a DTE in the device table in the system memory and flushing a corresponding DTE of the DTE cache in the host bridge.

5. The method according to claim 4, further comprises synchronizing the PCI instruction with the flushing of the DTE.

6. The method according to claim 1, further comprises updating error state bits in the device table in the system memory and the DTE cache.

7. The method according to claim 1, wherein the method further comprises load response handling comprising:

blocking by the host bridge of all load responses based on a DTE being in an error state;

blocking by the processor of all load responses based on a DTE being in an error state and receiving an indication to check by the host bridge;

checking by the host bridge of the error state in the DTE cache based on the DTE for a load response being cached; and

clearing an error state in the DTE.

8. A computer program product for implementing a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising;

accessing the device table in the system memory by the host bridge;

managing a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes; and

maintaining a usage count and an in-use count in the host bridge for each cached DTE.

9. The computer program product according to claim 8, wherein the device table in the system memory has at least 3 orders of magnitude more entries than the DTE cache and the DTE cache is accessed for DMA operations.

10. The computer program product according to claim 8, wherein, for a PCI instruction, the method further comprises:

updating a DTE in the device table in the system memory;

flushing a corresponding DTE in the DTE cache in the host bridge; and

synchronizing the PCI instruction with the flushing of the DTE.

11. The computer program product according to claim 8, wherein the method further comprises updating error state bits in the device table in the system memory and the DTE cache.

12. The computer program product according to claim 8, wherein the method further comprises load response handling comprising:

blocking by the host bridge of all load responses based on a DTE being in an error state;

blocking by the processor of all load responses based on a DTE being in an error state and receiving an indication to check by the host bridge;

checking by the host bridge of the error state in the DTE cache based on the DTE for a load response being cached; and

clearing an error state in the DTE.

13. A computer system for implementing a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge, the system comprising:

a memory having computer readable instructions; and

a processor configured to execute the computer readable instructions, the instructions comprising;

an access instruction that the device table in the system memory is accessed by the host bridge;

a manage instruction that a device table entry (DTE) cache is managed in the host bridge for coherency for DTE configuration changes; and

a count instruction that a usage count and an in-use count are maintained in the host bridge for each cached DTE.

14. The system according to claim 13, wherein the device table in the system memory has at least 3 orders of magnitude more entries than the DTE cache.

15. The system according to claim 13, wherein the DTE cache is accessed for DMA operations.

16. The system according to claim 13, wherein, for a PCI instruction, a DTE in the device table in the system memory is updated and a corresponding DTE in the DTE cache in the adapter is flushed.

17. The system according to claim 16, wherein the PCI instruction is synchronized with the flushing of the DTE.

18. The system according to claim 13, wherein error state bits are updated in the device table in the system memory and the DTE cache.

19. The system according to claim 13, wherein the instructions further comprises a load response handling instruction comprising:

a block by the host bridge of all load responses based on a DTE being in an error state; and

a block by the processor of all load responses based on a DTE being in an error state and receiving an indication to check by the host bridge;

a check by the host bridge of the error state in the DTE cache based on the DTE for a load response being cached.

20. The system according to claim 19, wherein the instructions further comprise a clear instruction that an error state in the DTE.