BIT PLANE MEMORY SYSTEM

• US 20150262557A1
• Filed: 03/12/2015
• Published: 09/17/2015
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: Christie Digital Systems USA Incorporated (Ushio Incorporated)
• Original Assignee: Brass Roots Technologies, LLC (Ushio Incorporated)
• Inventors: Walker, Bradley William, Fritz, Matthew John
• Granted Patent: US 9,858,902 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 5/937 by assembling picture element blocks in an intermediate store

Abstract

A data processing system comprising a transpose system configured to receive video ordered pixel data and to generate bit plane blocks of data. A write buffer configured to receive the bit plane blocks of data and to generate bit plane data frames. A memory controller configured to receive the bit plane data frames and to write a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory. A read buffer configured to receive the second bit plane data frame and to convert the second bit plane data frame to a digital display device format.

Claims

1. A data processing system comprising:

a transpose system configured to receive video ordered pixel data and to generate bit plane blocks of data;

a write buffer configured to receive the bit plane blocks of data and to generate bit plane data frames;

a memory controller configured to receive the bit plane data frames and to write a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory; and

a read buffer configured to receive the second bit plane data frame and to convert the second bit plane data frame to a digital display device format.

2. The data processing system of claim 1 wherein the memory is no larger than two frames of video data.

3. The data processing system of claim 1 wherein the memory comprises a DDR3 SDRAM block.

4. The data processing system of claim 1 wherein the memory controller uses a scatter reading and writing process to write the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from the memory.

5. The data processing system of claim 1 wherein the write buffer is coupled to a first pixel clock and to a second memory clock.

6. The data processing system of claim 5 wherein a first pixel clock rate is different from a second memory clock rate.

7. The data processing system of claim 1 wherein the read buffer is coupled to a first memory clock and to a second display clock.

9. The data processing system of claim 1 wherein the transpose system further comprises:

a plurality of delays; and

a barrel shifting circuit coupled to the plurality of delays.

10. The data processing system of claim 1 wherein the transpose system further comprises:

a first plurality of delays;

a barrel shifting circuit having an input coupled to the first plurality of delays and an output; and

a second plurality of delays coupled to the barrel shifting circuit.

11. The data processing system of claim 1 wherein the transpose system further comprises:

a first delay having a delay value of zero;

a second delay having a delay value of one; and

a barrel shifting circuit coupled to the first delay and the second delay.

12. The data processing system of claim 1 wherein the write buffer is coupled to a first pixel clock and to a second memory clock, and the read buffer is coupled to the second memory clock and to a third display clock.

14. The data processing system of claim 1 wherein the transpose buffer comprises a plurality of parallel transpose buffers that each receive a separate stream of video ordered pixel data.

19. The method of claim 1 wherein generating the bit plane blocks of data with the transpose system comprises:

delaying different bits of the video ordered pixel data with a plurality of delays; and

shifting the different bits of the delayed video ordered pixel data with a barrel shifting circuit.

8. The data processing system of claim 8 wherein a first memory clock rate is different from a second display clock rate.

13. The data processing system of claim 8 wherein a first memory clock rate is different from a second display clock rate, and a third display clock rate is different from the first memory clock rate and the second display clock rate.

15. A method for processing data comprising:

receiving video ordered pixel data at a transpose system and generating bit plane blocks of data with the transpose system;

receiving the bit plane blocks of data at a write buffer and generating bit plane data frames with the write buffer;

receiving the bit plane data frames at a memory controller and writing a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory using the memory controller; and

receiving the second bit plane data frame at a read buffer and converting the second bit plane data frame to a digital display device format using the read buffer.

16. The method of claim 15 wherein writing the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from memory using the memory controller comprises using a scatter reading and writing process to write the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from the memory.

17. The method of claim 15 further comprising receiving a first pixel clock signal and a second memory clock signal at the write buffer.

18. The method of claim 17 wherein the first pixel clock signal is received at a different rate than the second memory clock rate signal.

20. In a data processing system having a transpose system configured to receive video ordered pixel data and to generate bit plane blocks of data, a write buffer configured to receive the bit plane blocks of data and to generate bit plane data frames, a memory controller configured to receive the bit plane data frames and to write a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory, a read buffer configured to receive the second bit plane data frame and to convert the second bit plane data frame to a digital display device format, wherein the memory is no larger than two frames of video data, wherein the memory comprises a DDR3 SDRAM block, wherein the memory controller uses a scatter reading and writing process to write the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from the memory, wherein the write buffer is coupled to a first pixel clock and to a second memory clock, wherein a first pixel clock rate is different from a second memory clock rate, wherein the read buffer is coupled to a first memory clock and to a second display clock, wherein a first memory clock rate is different from a second display clock rate, wherein the transpose system includes a plurality of delays, a barrel shifting circuit coupled to the plurality of delays, and a second plurality of delays coupled to the barrel shifting circuit, wherein the plurality of delays includes a first delay having a delay value of zero and a second delay having a delay value of one, wherein the write buffer is coupled to a first pixel clock and to a second memory clock, and the read buffer is coupled to the second memory clock and to a third display clock, and wherein the transpose buffer comprises a plurality of parallel transpose buffers that each receive a separate stream of video ordered pixel data, a method, comprising:

receiving the video ordered pixel data at the transpose system and generating the bit plane blocks of data with the transpose system;

receiving the bit plane blocks of data at the write buffer and generating the bit plane data frames with the write buffer;

receiving the bit plane data frames at the memory controller and writing the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from memory using the memory controller;

receiving the second bit plane data frame at a read buffer and converting the second bit plane data frame to a digital display device format using the read buffer;

wherein writing the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from memory using the memory controller comprises using the scatter reading and writing process to write the first bit plane data frame to the memory while simultaneously reading the second bit plane data frame from the memory;

receiving the first pixel clock signal and the second memory clock signal at the write buffer;

wherein the first pixel clock signal is received at a different rate than the second memory clock rate signal; and

wherein generating the bit plane blocks of data with the transpose system comprises;

delaying different bits of the video ordered pixel data with the plurality of delays; and

shifting the different bits of delayed video ordered pixel data with the barrel shifting circuit.