ACCESS COUNT DEVICE, MEMORY SYSTEM, AND ACCESS COUNT METHOD

• US 20150262652A1
• Filed: 03/16/2015
• Published: 09/17/2015
• Est. Priority Date: 03/17/2014
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: IGARASHI, Kenichi
• Application Number:
  US14/658,397
• Publication Number:
  US 20150262652A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/408 Address circuits

Abstract

An access count device and the like in a semiconductor memory are disclosed, which count accesses to row addresses in the semiconductor memory with a smaller circuit scale. An access count device includes a row-address storage unit configured to store up to a specific number n (n is an integer equal to or more than 1) of row addresses specified in accesses to memory cells, a counter configured to count an access frequency to each row address stored in the row-address storage unit, and a reset controller configured to notify the row-address storage unit to replace one of the n row addresses with a new row address or discard one of the n row addresses, and also configured to notify the counter to reset an access frequency to the row address replaced or discarded.

Claims

1. An access count device comprising:

a row-address storage unit that stores up to a specific number n (n is an integer equal to or more than

     1) of row addresses specified in accesses to memory cells;

a counter that counts an access frequency to each row address stored in the row-address storage unit; and

a reset controller that notifies the row-address storage unit to replace one of the n row addresses with a new row address or discard one of the n row addresses, and also that notifies the counter to reset an access frequency to the row address replaced or discarded.

2. The access count device according to claim 1, further comprising

a row address selector that selects one of the n row addresses, based on the access frequency, if an access occurs, which specifies a new row address other than the n row addresses stored in the row-address storage unit,

wherein the reset controller notifies the row-address storage unit to store the new row address by replacing the row address selected by the row address selector with the new row address, and also that notifies the counter to reset an access frequency to the replaced row address.

3. The access count device according to claim 1, wherein the reset controller notifies the row address storage unit to discard a row address the access frequency to which reaches a specific allowable number of accesses, and also notifies the counter to reset the access frequency to the discarded row address.

4. The access count device according to claim 2, wherein the row address selector selects one of the n row addresses the access frequency to the one of the n row addresses meets a specific low frequency condition.

5. The access count device according to claim 2, further comprising m sets (m is an integer equal to or more than 2) of a combination of the row-address storage unit, the counter, the row address selector, and the reset controller, wherein the row addresses specified in the accesses are stored in the row-address storage unit of each set, and

wherein the row address selector in each set applies a selection condition differing from selection conditions applied by other sets, as a selection condition for selecting one of the n row addresses, based on the access frequency, if an access occurs, which specifies a new row address other than the n row addresses stored in the row-address storage unit in a same set as the set in which the row address selector applies the selection condition.

6. The access count device according to claim 5, wherein the row address selector in one of the m sets applies a specific low frequency condition as the selection condition, and wherein the row address selector in each of other sets applies a specific high frequency condition as the selection condition.

7. The access count device according to claim 1, wherein the n is a value based on a refresh interval, an access cycle, and the allowable number of accesses.

8. The access count device according to claim 1, further comprising an intensive access detector that detects a row address the access frequency to which reaches the allowable number of accesses.

9. A memory system comprising:

an access count device according to claim 1; and

a memory cell including the memory cells.

10. An access count method comprising:

storing up to a specific number n (n is an integer equal to or more than

     1) of row addresses specified in accesses to memory cells;

counting an access frequency to each of the stored row addresses;

replacing one of the n row addresses with a new row address or discarding the one of the n row addresses; and

resetting the access frequency to the row address replaced or discarded.