SEMICONDUCTOR MEMORY DEVICE AND MEMORY CONTROLLER
First Claim
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1. A semiconductor memory device, comprising:
- a plurality of string units, each of which includes a plurality of strings of memory cells connected in series;
a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit; and
a control circuit including a register that stores erase characteristic for at least one of the string units,wherein the control circuit is configured to output the erase characteristic in response to a command from a memory controller.
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Abstract
A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register that stores erase characteristic for at least one of the string units. The control circuit is configured to output the erase characteristic in response to a command from a memory controller.
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Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a plurality of string units, each of which includes a plurality of strings of memory cells connected in series; a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit; and a control circuit including a register that stores erase characteristic for at least one of the string units, wherein the control circuit is configured to output the erase characteristic in response to a command from a memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory controller that controls a semiconductor memory device including a plurality of string units, each of which includes a plurality of strings of memory cells are connected in series, the memory controller comprising:
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a control unit capable of issuing a command for reading an erase characteristic of each of the string units from the semiconductor memory device; and a storage unit that stores the erase characteristic for each string unit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of managing erase characteristics of a semiconductor memory device having a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register, said method comprising:
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performing an erase operation that includes an erase verify operation; storing an erase characteristic for at least one of the string units in the register, the erase characteristic for each string unit including an erase loop frequency at the time the string unit passed the erase verify operation; and outputting the erase characteristic in response to a command from a memory controller. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification