SEMICONDUCTOR MEMORY DEVICE AND MEMORY CONTROLLER

• US 20150262699A1
• Filed: 08/27/2014
• Published: 09/17/2015
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIRAKAWA, Masanobu
• Granted Patent: US 9,524,792 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register that stores erase characteristic for at least one of the string units. The control circuit is configured to output the erase characteristic in response to a command from a memory controller.

Claims

1. A semiconductor memory device, comprising:

a plurality of string units, each of which includes a plurality of strings of memory cells connected in series;

a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit; and

a control circuit including a register that stores erase characteristic for at least one of the string units,

wherein the control circuit is configured to output the erase characteristic in response to a command from a memory controller.

2. The device according to claim 1, wherein

the register includes a plurality of latch circuits which are connected in series, and

whenever any one of the string units passes an erase verify operation, information which identifies the string unit that passed the erase verify operation, and an erase loop frequency at time the string unit passed the erase verify operation are latched in the latch circuit.

3. The device according to claim 2, wherein

the register stores erase characteristic for each of N (N>

1) string units and includes N latch circuits, one for each of the string units.

4. The device according to claim 1, wherein

when a first erase command is received from the memory controller, all of the string units become an erase verify operation target, and

when a second erase command is received from the memory controller, only one of the string units within the block becomes an erase verify operation target.

5. The device according to claim 4, wherein

when the first erase command is issued, any string unit that is a bad string is not an erase verify operation target.

6. The device according to claim 4, wherein

the one string unit that becomes the erase verify operation target is selected according to the erase characteristic thereof.

7. The device according to claim 6, wherein

the erase characteristic includes erase loop frequency and the selected string unit has the highest erase loop frequency among all of the string units.

8. A memory controller that controls a semiconductor memory device including a plurality of string units, each of which includes a plurality of strings of memory cells are connected in series, the memory controller comprising:

a control unit capable of issuing a command for reading an erase characteristic of each of the string units from the semiconductor memory device; and

a storage unit that stores the erase characteristic for each string unit.

9. The controller according to claim 8, wherein

the erase characteristic for each string unit includes an erase loop frequency at the time the string unit passed an erase verify operation.

10. The controller according to claim 9, wherein

the memory controller causes all of the string units to be an erase verify operation target when the memory controller issues a first command, and

the memory controller causes only one of the string units to be an erase verify operation target when the memory controller issues a second command.

11. The controller according to claim 10, wherein

the one string unit that becomes the erase verify operation target is selected according to the erase characteristic thereof.

12. The controller according to claim 11, wherein

the selected string unit has the highest erase loop frequency among all of the string units.

13. The controller according to claim 10, wherein

the control unit is configured to periodically update a selection of the string unit which becomes the erase verify operation target when the memory controller issues the second command.

14. The controller according to claim 13, wherein

the control unit is configured to increase a frequency for updating the selection of the string unit which becomes the erase verify operation target as an erase frequency of the string units increases.

15. A method of managing erase characteristics of a semiconductor memory device having a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register, said method comprising:

performing an erase operation that includes an erase verify operation;

storing an erase characteristic for at least one of the string units in the register, the erase characteristic for each string unit including an erase loop frequency at the time the string unit passed the erase verify operation; and

outputting the erase characteristic in response to a command from a memory controller.

16. The method according to claim 15, wherein

the register includes a plurality of latch circuits which are connected in series, and

whenever any one of the string units passes the erase verify operation, information which identifies the string unit that passed the erase verify operation, and an erase loop frequency at time the string unit passed the erase verify operation are latched in the latch circuit.

17. The method according to claim 16, wherein

the register stores erase characteristic for each of N (N>

1) string units and includes N latch circuits, one for each of the string units.

18. The method according to claim 15, wherein

when a first erase command is received from the memory controller, all of the string units become an erase verify operation target, and

when a second erase command is received from the memory controller, only one of the string units within the block becomes an erase verify operation target.

19. The method according to claim 18, further comprising:

selecting the one string unit that becomes the erase verify operation target according to the erase characteristic thereof.

20. The method according to claim 19, wherein

the selected string unit has the highest erase loop frequency among all of the string units.