CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS

• US 20150262812A1
• Filed: 05/13/2014
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Wen-Kuei, Tsai, Teng-Chun, Liao, Kao-Feng, Yen, Yu-Ting, Su, Yu-Chung
• Granted Patent: US 9,281,192 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31133 by chemical means
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

Claims

1. A method of manufacturing an integrated circuit device, comprising:

processing a wafer through a series of operations to form a topographically variable layer of a material on the wafer, wherein the layer varies in height across the wafer;

spin coating a monomer-containing solvent solution over a surface of the layer of the material;

heating the wafer to within a first temperature range;

maintaining the wafer within the first temperature range while the majority of the solvent evaporates from the solution;

heating the wafer to within a second temperature range that is above the first temperature range;

maintaining the wafer within the second temperature range until the monomers have polymerized to form a polymer coating and the polymers in the coating have cross-linked;

chemically mechanically polishing to remove a first portion of the polymer coating; and

etching to effectuate a top-down recessing of the polymer coating.

2. The method of claim 1, wherein the heating of the substrate to within the first temperature range is heating the substrate on a hot plate within a chamber

3. The method of claim 2, further comprising:

while maintaining the wafer within the first temperature range and while the majority of the solvent is evaporating from the solution, exhausting the chamber from an outlet below the wafer.

4. The method of claim 2, further comprising:

while maintaining the wafer within the first temperature range and while the majority of the solvent is evaporating from the solution, providing a gas flow through the chamber, wherein the gas flow enters the chamber from above the wafer and exists the chamber below the wafer.

5. The method of claim 4, wherein the gas flow exits the wafer through a port centered below the wafer.

6. The method of claim 1, wherein the etching to effectuate a top-down recessing of the polymer coating is etching with a low selectivity between the polymer and the material and effectuates a top-down recessing of the layer of the material.

7. The method of claim 1, wherein the chemical mechanical polishing stops on the layer of the material.

8. The method of claim 6, wherein the etching recesses the polymer coating and the layer of the material within a dielectric layer on the surface.

9. The method of claim 1, wherein the spin coating, the chemical mechanical polishing, and the etching with a low selectivity take place within and form part of a replacement gate process.

10. The method of claim 1, wherein the layer of the material is a layer of a hard mask.

11. The method of claim 1, wherein the layer of the material is a work function metal that forms part of a metal gate electrode.

12. The method of claim 11, wherein the spin coating of the monomer-containing solvent solution places the solution in direct contact with the work function metal.

13. The method of claim 11, wherein the metal gate electrode is formed over one or more finFET fins.

14. The method of claim 1, further comprising:

after the etching to effectuate a top-down recessing of the polymer coating, etching with a high selectivity between the material and the polymer coating to recess the layer of the material.

15. The method of claim 1, wherein the polymer coating is a photoresist.

16. The method of claim 1, wherein:

the first temperature range is below a minimum temperature at which the polymer undergoes thermal cross-linking at a significant rate;

the second temperature range is above the minimum temperature at which the polymer undergoes thermal cross-linking at a significant rate.

17. A method of manufacturing an integrated circuit device, comprising:

forming a topographically variable layer of a material on a wafer, wherein the layer varies in height across the wafer;

coating a monomer-containing solvent solution over the layer of the material;

heating the wafer on a hot plate in a chamber while the majority of the solvent evaporates from the solution coated over the layer of the material, the monomers in the solution form polymers, and the polymers cross-link to form a cross-linked polymer coating;

while the majority of the solvent evaporates from the solution coated over the layer of the material, flowing a gas through the chamber, wherein the gas flow enters the chamber above the wafer and exits the chamber below the wafer;

chemically mechanically polishing to remove a first portion of the polymer coating; and

etching to effectuate a top-down recessing of the polymer coating.

18. The method of claim 17, wherein the heating of the wafer on the hot plate in the chamber comprises:

heating the wafer to within a first temperature range;

maintaining the wafer within the first temperature range while the majority of the solvent evaporates from the solution;

heating the wafer to within a second temperature range that is above the first temperature range;

maintaining the wafer within the second temperature range until the monomers have polymerized to form a polymer coating and the polymers in the coating have cross-linked.

19. The method of claim 18, wherein:

the first temperature range is below a minimum temperature at which the polymer undergoes thermal cross-linking at a significant rate;

the second temperature range is above the minimum temperature at which the polymer undergoes thermal cross-linking at a significant rate.

20. A method of manufacturing an integrated circuit device, comprising:

forming finFETs having dummy gates having a height and wrapping fins on a semiconductor substrate;

forming a first dielectric layer that covers the semiconductor substrate and has a height at least equal to the height of the dummy gates;

removing the dummy gates to form trenches that are within the first dielectric layer;

forming a layer of a work function metal over a channel region of some of the fins, wherein the layer of the work function metal lines at least a portion of the length of at least some of the trenches, whereby the layer of the work function metal rises to the tops of the trenches at some locations;

forming a polymer coating above the layer of the work function metal, wherein the polymer fills the trenches and forming the polymer coating comprises;

spin coating with a monomer-containing solvent solution;

heating the semiconductor substrate to within a first temperature range;

maintaining the semiconductor substrate within the first temperature range while the majority of the solvent evaporates from the solution;

heating the semiconductor substrate to within a second temperature range that is above the first temperature range;

maintaining the semiconductor substrate within the second temperature range until the monomers have polymerized to form the polymer coating and the polymers in the coating have cross-linked;

chemically mechanically polishing to form a planar upper surface comprising the polymer; and

after the chemical-mechanical polishing, plasma etching, wherein the plasma etching causes the polymer to become recessed within the trenches.