METHOD FOR FORMING WIRING

• US 20150262864A1
• Filed: 08/20/2013
• Published: 09/17/2015
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Nanobridge Semiconductor Incorporated
• Original Assignee: NEC Corporation
• Inventors: Okamoto, Koichiro, Tada, Munehiro, Hada, Hiromitsu, Sakamoto, Toshitsugu
• Granted Patent: US 9,245,789 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO₂ layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.

Claims

1. A wiring forming method comprising:

forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer insulating film that has a via hole which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising, at least, an SOC layer, an SOG layer, an SiO₂ layer, and a chemically amplification type resist superposed in this order from the substrate side;

conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and

forming the wiring layer and the via plugs in the pattern.

2. The wiring forming method according to claim 1, wherein

an SiCN film or an SiN film is exposed at a bottom of the via hole, and a lower layer of the film is made of at least one of WN, TaN and TiN.

3. The wiring forming method according to claim 1, wherein

the SiO₂ layer is a high density SiO₂ layer whose density is 2.1 g/cm³ or higher.

4. The wiring forming method according to claim 3, wherein

the high density SiO₂ layer is formed by use of the high density plasma whose electron density is 10¹⁰ electrons/cm³ or higher.

5. The wiring forming method according to claim 3, wherein

the high density SiO₂ layer is formed under the condition that a substrate temperature is 250°

C. or lower to 150°

C. or higher.

6. The wiring forming method according to claim 1, wherein

after raw material of organic silica is applied on the substrate which is rotated, the SOG layer is formed by carrying out thermal treatment.

7. The wiring forming method according to claim 1, wherein

a total of thicknesses of the SOG layer and the SiO₂ layer is 100 nm or less to 50 nm or more.

8. The wiring forming method according to claim 7, wherein

a thickness of the SOG layer is in an range of 15 nm to 60 nm, and a thickness of the SiO₂ layer is in an range of 30 nm to 80 nm.

9. The wiring forming method according to claim 4, wherein

the high density plasma (HDP) includes, at least, raw material of silane and oxidizing gas.

10. The wiring forming method according to claim 9, wherein

the high density plasma (HDP) includes, at least, SiH₄, N₂O and Ar.