INTERPOSERS WITH CIRCUIT MODULES ENCAPSULATED BY MOLDABLE MATERIAL IN A CAVITY, AND METHODS OF FABRICATION

• US 20150262928A1
• Filed: 12/02/2014
• Published: 09/17/2015
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Shen, Hong, Wang, Liang, Katkar, Rajesh
• Granted Patent: US 9,324,626 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Stacked dies (110) are encapsulated in an interposer'"'"'s cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity'"'"'s bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Claims

1. A circuit assembly comprising a plurality of levels L0 through Ln wherein n is an integer greater than one, the circuit assembly comprising a substrate whose top side comprises a cavity comprising a bottom wall;

wherein the level L0 comprises;

the bottom wall;

a plurality of through-holes each of which passes through the bottom wall;

a plurality of conductors “

L0 conductors”

) in respective through-holes;

wherein for each level Li other than L0 and L1;

at least part of level Li overlies at least part of level Li−

1;

each level Li comprises one or more circuit modules each of which has one or more contact pads each of which is electrically connected to one or more L0 conductors by one or more first electrically conductive paths lying in the cavity.

2. The circuit assembly of claim 1 wherein the substrate comprises:

a first substrate comprising the bottom wall; and

a second substrate comprising sidewalls of the cavity, the second substrate being attached to the first substrate;

wherein an interface region of the first and second substrates is not uniform with respect to at least one of;

chemical composition, density, elasticity modulus, conductivity, dielectric constant, ultrasound propagation speed for one or more wavelengths, light propagation speed for one or more wavelengths not exceeding an infrared wavelength.

3. The circuit assembly of claim 1 further comprising a plurality of first encapsulant layers made of a moldable material, wherein each level L1 through Ln−

1 comprises at least one first encapsulant layer laterally encapsulating the one or more circuit modules at that level.

4. The circuit assembly of claim 3 wherein at least a first portion of each first encapsulant layer rises at least as high as a top surface of at least one circuit module laterally encapsulated by the first encapsulant layer;

wherein at least the first portion of each first encapsulant layer reaches down at least as low as a bottom surface of at least one circuit module laterally encapsulated by the first encapsulant layer;

wherein at least the first portion of each first encapsulant layer is formed in a single curing operation with no separately cured sub-layers.

5. The circuit assembly of claim 4 wherein for each first electrically conductive path passing through any first encapsulant layer, the first electrically conductive path comprises a vertical segment passing through the first encapsulant layer.

6. The circuit assembly of claim 3 wherein at least one level Li with i greater than 0 comprises at least one horizontal segment in at least one first electrically conductive path passing through the level'"'"'s first encapsulant layer, the horizontal segment being below the level'"'"'s first encapsulant layer.

7. The circuit assembly of claim 6 wherein the horizontal segment overlies the first encapsulation layer of the level Li−

1 and at least one die of the level Li−

1, the die being covered by the first encapsulation layer of the level Li−

1.

8. The circuit assembly of claim 3 further comprising one or more second electrically conductive paths in the cavity, wherein each second electrically conductive path does not have electrical functionality but is for enhancing heat removal from the circuit assembly to the ambient, wherein each second electrically conductive path extends from an L0 conductor through one or more levels other than L0 and for each level other than L0.

9. The circuit assembly of claim 3 wherein each first encapsulant layer has a planar top surface.

10. The circuit assembly of claim 1 wherein each through-hole through the bottom wall is vertical, and each L0 conductor is vertical.

11. A manufacturing method comprising:

obtaining a structure comprising;

a substrate whose top side comprises a cavity comprising a bottom wall, the substrate comprising a plurality of through-holes (“

L0 through-holes”

) each of which passes through the bottom wall;

a plurality of conductors “

L0 conductors”

) each of which passes through a respective L0 through-hole;

a conductive layer underlying the bottom wall and electrically connected to each L0 conductor;

attaching one or more circuit modules (“

L1 circuit modules”

) to a bottom of the cavity to electrically connect one or more contact pads of each L1 circuit module to one or more L0 conductors;

forming an encapsulant layer (“

L1 encapsulant layer”

) of a moldable material to laterally encapsulate the one or more L1 circuit modules;

forming one or more through-holes (“

L1 through-holes”

) in the L1 encapsulant layer, each L1 through-hole exposing a feature provided by, or electrically connected to, at least one L0 conductor; and

electroplating conductive material into the L1 through-holes onto the features exposed by the L1 through-holes, to form one or more L1 conductors, each L1 conductor passing through a respective L1 through-hole, wherein the electroplating comprises providing an electroplating current flowing through the features, the L0 conductors, the conductive layer, and a terminal of an electric power source coupled to the conductive layer.

12. The method of claim 11 wherein the substrate comprises:

a first substrate comprising the bottom wall; and

a second substrate comprising sidewalls of the cavity, the second substrate being attached to the first substrate; and

obtaining the structure comprises attaching the first substrate to the second substrate to provide said substrate.

13. The method of claim 11 further comprising forming a redistribution layer on the bottom of the cavity, wherein said features are at a top of the redistribution layer, the redistribution layer electrically connecting the features to the L0 conductors.

14. The method of claim 11 further comprising:

attaching one or more circuit modules (“

L2 circuit modules”

) inside the cavity to electrically connect one or more contact pads of each L2 circuit module to one or more L1 conductors;

forming an encapsulant layer (“

L2 encapsulant layer”

) of a moldable material to laterally encapsulate the one or more L2 circuit modules;

forming one or more through-holes (“

L2 through-holes”

) in the L2 encapsulant layer, each L2 through-hole exposing a feature provided by, or electrically connected to, at least one L1 conductor; and

electroplating conductive material into the L2 through-holes onto the features exposed by the L2 through-holes, to form a plurality of L2 conductors, each L2 conductor passing through a respective L2 through-hole, wherein the electroplating comprises providing an electroplating current flowing through the L1 conductors, the L0 conductors, the conductive layer, and a terminal of an electric power source coupled to the conductive layer.

15. A circuit assembly comprising:

a substrate whose top side comprises a cavity comprising a bottom wall;

a plurality of through-holes each of which passes through the bottom wall;

a plurality of conductors in respective through-holes;

a plurality of circuit modules in the cavity, each circuit module having one or more contact pads;

a plurality of first encapsulant layers overlying one another in the cavity, wherein each first encapsulant layer is made of a moldable material and laterally encapsulates one or more of the circuit modules;

a plurality of first electrically conductive paths each of which lies in the cavity and passes through one or more first encapsulant layers to connect at least one contact pad of at least one circuit module to at least conductor passing through the bottom wall.

16. The circuit assembly of claim 15 wherein the substrate comprises:

a first substrate comprising the bottom wall; and

a second substrate comprising sidewalls of the cavity, the second substrate being attached to the first substrate;

wherein an interface region of the first and second substrates is not uniform with respect to at least one of;

chemical composition, density, elasticity modulus, conductivity, dielectric constant, ultrasound propagation speed for one or more wavelengths, light propagation speed for one or more wavelengths not exceeding an infrared wavelength.

17. The circuit assembly of claim 15 wherein at least a first portion of each first encapsulant layer rises at least as high as a top surface of at least one circuit module laterally encapsulated by the first encapsulant layer;

wherein at least the first portion of each first encapsulant layer reaches down at least as low as a bottom surface of at least one circuit module laterally encapsulated by the first encapsulant layer;

wherein at least the first portion of each first encapsulant layer is formed in a single curing operation with no separately cured sub-layers.

18. The circuit assembly of claim 17 wherein each encapsulant layer has a planar top surface.

19. The circuit assembly of claim 15 further comprising one or more horizontal electrically conductive interconnects each of which belongs to at least one first electrically conductive path passing through a first encapsulant layer overlying the horizontal electrically conductive interconnect.

20. The circuit assembly of claim 15 further comprising one or more second electrically conductive paths in the cavity, wherein each second electrically conductive path does not have electrical functionality but is for enhancing heat removal from the circuit assembly to the ambient, wherein each second electrically conductive path begins at a conductor in the through-hole and extends through one or more of the encapsulant layers.

21. The circuit assembly of claim 15 wherein each through-hole through the bottom wall is vertical, and each conductor in each through-hole in the bottom wall is vertical.